am79c972b Advanced Micro Devices, am79c972b Datasheet - Page 123

• Manufacturer Part Number: am79c972b
• Description: Pcnet?-fast+ Enhanced 10/100 Mbps Pci Ethernet Controller With Onnow Support
• Manufacturer: Advanced Micro Devices

CSR20: Current Transmit Buffer Address Lower
Bit
31-16
15-0
CSR21: Current Transmit Buffer Address Upper
Bit
31-16
15-0
CSR22: Next Receive Buffer Address Lower
Bit
31-16
15-0
Name
RES
CXBAL
Name
RES
CXBAU
Name
NRBAL
RES
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
next receive buffer address to
which the Am79C972 controller
will store incoming frame data.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Description
Reserved locations. Written as
zeros and read as undefined.
Contains the lower 16 bits of the
current transmit buffer address
from which the Am79C972 con-
troller is transmitting.
Description
Reserved locations. Written as
zeros and read as undefined.
Contains the upper 16 bits of the
current transmit buffer address
from which the Am79C972 con-
troller is transmitting.
Description
Reserved locations. Written as
zeros and read as undefined.
Contains the lower 16 bits of the
Am79C972
CSR23: Next Receive Buffer Address Upper
Bit
31-16 RES
15-0
CSR24: Base Address of Receive Ring Lower
Bit
31-16 RES
15-0
CSR25: Base Address of Receive Ring Upper
Bit
31-16 RES
15-0
CSR26: Next Receive Descriptor Address Lower
Bit
31-16 RES
15-0
Name
NRBAU
Name
BADRL
Name
BADRU
Name
NRDAL
zeros and read as undefined.
next receive buffer address to
which the Am79C972 controller
will store incoming frame data.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
zeros and read as undefined.
base address of the Receive
Ring.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
zeros and read as undefined.
base address of the Receive
Ring.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
zeros and read as undefined.
next receive descriptor address
pointer.
Description
Reserved locations. Written as
Contains the upper 16 bits of the
Description
Reserved locations. Written as
Contains the lower 16 bits of the
Description
Reserved locations. Written as
Contains the upper 16 bits of the
Description
Reserved locations. Written as
Contains the lower 16 bits of the
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