am79c972b Advanced Micro Devices, am79c972b Datasheet - Page 78

• Manufacturer Part Number: am79c972b
• Description: Pcnet?-fast+ Enhanced 10/100 Mbps Pci Ethernet Controller With Onnow Support
• Manufacturer: Advanced Micro Devices

AMD Flash Programming
AMD’s Flash products are programmed on a byte-by-
byte basis. Programming is a four bus cycle operation.
There are two “unlock” write cycles. These are followed
by the program set-up command and data write cycles.
Addresses are latched on the falling edge of EBWE
and the data is latched on the rising edge of EBWE.
The rising edge of EBWE begins programming.
Upon executing the AMD Flash Embedded Program
Algorithm command sequence, the Am79C972 con-
troller is not required to provide further controls or tim-
ing. The AMD Flash product will compliment EBD[7]
during a read of the programmed location until the pro-
gramming is complete. The host software should poll
the programmed address until EBD[7] matches the
programmed value.
AMD Flash byte programming is allowed in any se-
quence and across sector boundaries. Note that a data
0 cannot be programmed back to a 1. Only erase oper-
ations can convert zeros to ones. AMD Flash chip
erase is a six-bus cycle operation. There are two unlock
write cycles, followed by writing the set-up command.
Two more unlock cycles are then followed by the chip
erase command. Chip erase does not require the user
to program the device prior to erasure. Upon executing
78
Byte Program
Sector Erase
Command
Chip Erase
Sequence
Cycles
Req’d
Write
Bus
4
6
6
EBUA_EBA[7:0]
5555h
5555h
5555h
EBDA[15:8]
Addr
Write Cycle
AS_EBOE
First Bus
EROMCS
Figure 44. Flash Write from Expansion Bus Data Port
EBD[7:0]
EBWE
CLK
Data
AAh
AAh
AAh
Table 9. Am29Fxxx Flash Command
2AAAh
2AAAh
2AAAh
Second Bus
Addr
Write Cycle
EBUA[19:16]
1
Data
55H
55H
55H
Am79C972
2
5555h
5555h
5555h
3
Addr
Write Cycle
Third Bus
4
the AMD Flash Embedded Erase Algorithm command
sequence, the Flash device will program and verify the
entire memory for an all zero data pattern prior to elec-
trical erase. The Am79C972 controller is not required
to provide any controls or timings during these opera-
tions. The automatic erase begins on the rising edge of
the last EBWE pulse in the command sequence and
terminates when the data on EBD[7] is 1, at which time
the Flash device returns to the read mode. Polling by
the Am79C972 controller is not required during the
erase sequence. The following FLASH programming-
table excerpt (Table 9) shows the command sequence
for byte programming and sector/chip erasure on an
AMD Flash device. In the following table, PA and PD
stand for programmed address and programmed data,
and SA stands for sector address.
The Am79C972 controller will support only a single
sector erase per command and not concurrent sector
erasures. The Am79C972 controller will support most
FLASH devices as long as there is no timing require-
ment between the completion of commands. The
FLASH access time cannot be guaranteed with the
Am79C972 controller access mechanism. The
Am79C972 controller will also support only Flash de-
vices that do not require data hold times after write op-
erations.
Data
5
A0h
80h
80h
6
5555h
5555h
Addr
Write Cycle
Fourth Bus
7
EBDA[15:8]
PA
EBA[7:0]
8
Data
AAh
AAh
9
PD
10
2AAAh
2AAAh
Addr
Write Cycle
11
Fifth Bus
12 13
Data
55h
55h
5555h
Addr
Write Cycle
SA
Sixth Bus
21485C-47
Data
10h
3h