am79c972b Advanced Micro Devices, am79c972b Datasheet - Page 107

• Manufacturer Part Number: am79c972b
• Description: Pcnet?-fast+ Enhanced 10/100 Mbps Pci Ethernet Controller With Onnow Support
• Manufacturer: Advanced Micro Devices

10
9
RINT
TINT
When MERR is set, INTA is as-
serted if IENA is 1 and the mask
bit MERRM (CSR3, bit 11) is 0.
MERR assertion will set the ERR
bit, regardless of the settings of
IENA and MERRM.
Read/Write accessible always.
MERR is cleared by the host by
writing a 1. Writing a 0 has no ef-
fect.
H_RESET, S_RESET, or by set-
ting the STOP bit.
When RINT is set, INTA is assert-
ed if IENA is 1 and the mask bit
RINTM (CSR3, bit 10) is 0.
Read/Write accessible always.
RINT is cleared by the host by
writing a 1. Writing a 0 has no ef-
fect.
H_RESET, S_RESET, or by set-
ting the STOP bit.
When TINT is set, INTA is assert-
ed if IENA is 1 and the mask bit
TINTM (CSR3, bit 9) is 0.
TINT will not be set if TINTOKD
(CSR5, bit 15) is set to 1 and the
transmission was successful.
Read/Write accessible always.
TINT is cleared by the host by
writing a 1. Writing a 0 has no ef-
fect.
H_RESET, S_RESET, or by set-
ting the STOP bit.
Receive Interrupt is set by the
Am79C972 controller after the
last descriptor of a receive frame
has been updated by writing a 0
to the OWNership bit. RINT may
also be set when the first descrip-
tor of a receive frame has been
updated by writing a 0 to the
OWNership bit if the LAPPEN bit
of CSR3 has been set to a 1.
Transmit Interrupt is set by the
Am79C972 controller after the
OWN bit in the last descriptor of a
transmit frame has been cleared
to indicate the frame has been
sent or an error occurred in the
transmission.
MERR
RINT
TINT
is
is
is
cleared
cleared
cleared
Am79C972
by
by
by
8
7
6
5
IDON
INTR
IENA
RXON
Am79C972 controller after the
initialization sequence has com-
pleted. When IDON is set, the
Am79C972 controller has read
the initialization block from mem-
ory.
When IDON is set, INTA is as-
serted if IENA is 1 and the mask
bit IDONM (CSR3, bit 8) is 0.
Read/Write accessible always.
IDON is cleared by the host by
writing a 1. Writing a 0 has no ef-
fect.
H_RESET, S_RESET, or by set-
ting the STOP bit.
or more following interrupt caus-
ing conditions has occurred:
EXDINT, IDON, MERR, MISS,
MFCO, RCVCCO, RINT, SINT,
TINT, TXSTRT, UINT, STINT,
MREINT, MCCINT, MIIPDTINT,
MAPINT and the associated
mask or enable bit is pro-
grammed to allow the event to
cause an interrupt. If IENA is set
to 1 and INTR is set, INTA will be
active. When INTR is set by SINT
or SLPINT, INTA will be active in-
dependent of the state of IENA.
Read accessible always. INTR is
read only. INTR is cleared by
clearing all of the active individual
interrupt bits that have not been
masked out.
be active if the Interrupt Flag is
set. If IENA = 0, then INTA will be
disabled regardless of the state
of INTR.
Read/Write accessible always.
IENA is set by writing a 1 and
cleared by writing a 0. IENA is
cleared
S_RESET and setting the STOP
bit.
ceive function is enabled. RXON
is set if DRX (CSR15, bit 0) is set
to 0 after the START bit is set. If
INIT and START are set together,
Initialization Done is set by the
Interrupt Flag indicates that one
Interrupt Enable allows INTA to
Receive On indicates that the re-
IDON
by
is
H_RESET
cleared
107
by
or