bt8960 Mindspeed Technologies, bt8960 Datasheet - Page 79

• Manufacturer Part Number: bt8960
• Description: Bt8960, Single-chip 2b1q Transceiver
• Manufacturer: Mindspeed Technologies

Bt8960
Single-Chip 2B1Q Transceiver
3.2.63 0x77—Scratch Pad Write Tap Select (sp_tap_select_write)
A 6-bit read/write register representing an unsigned binary address defined over a range of 0 to 63 decimals.
When written, it causes the lowest-order 8 bits of the Access Data Register [access_data_byte[3:0]; 0x7C–
0x7F] to be subsequently written to the selected scratch pad memory location within two symbol periods. Does
not affect the value of the access data register.
3.2.64 0x78—Equalizer Read Select Register (eq_add_read)
A 6-bit read/write register representing an unsigned binary address defined over a range of 0 to 47 decimals.
When written, it causes the selected 16-bit location of the equalizer register file to be subsequently loaded into
the lowest-order bits of the Access Data Register [access_data_byte[3:0]; 0x7C–0x7F] within two symbol peri-
ods. Does not affect the value of the register file location. An address map of the shared register file, as defined
by the factory-delivered microcode, is shown below.
7
7
–
–
Decimal
16–20
21–25
35–47
8–15
0–7
26
27
28
29
30
31
32
33
34
6
6
–
–
D[5:0]
00 0000–00 0111
00 1000–00 1111
01 0000–01 0100
01 0101–01 1001
10 0011–10 1111
D[5]
D[5]
5
5
01 1010
01 1011
01 1100
01 1101
01 1110
01 1111
10 0000
10 0001
10 0010
Binary
D[4]
D[4]
4
4
N8960DSB
DAGC Gain - Least-Significant Word
DAGC Gain - Most-Significant Word
DAGC Output
FFE Output
DAGC Input
FFE Output, Delayed 1 Symbol Period
DAGC Error Signal
Equalizer Error Signal
Slicer Error Signal
FFE Coefficients 0–7
FFE Data Taps 0–7
EP Coefficients 0–4
EP Data Taps 0–4
Reserved
D[3]
D[3]
3
3
Stored Parameter
D[2]
D[2]
2
2
D[1]
D[1]
1
1
3.1 Conventions
3.0 Registers
D[0]
D[0]
0
0
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