bt8960 Mindspeed Technologies, bt8960 Datasheet - Page 66

• Manufacturer Part Number: bt8960
• Description: Bt8960, Single-chip 2b1q Transceiver
• Manufacturer: Mindspeed Technologies

56
3.0 Registers
3.1 Conventions
3.2.27 0x22—PLL Modes Register (pll_modes)
clk_freq[1,0]
gain[1,0]
freeze_pll
pll_gain[1,0]
phase_detector_
clk_freq[1]
7
clk_freq[0]
Clock Frequency Select—Read/write binary field specifies one of four data rate ranges for
Bt8960 operation. The 00 state is automatically selected by RST assertion and upon initial
power application. The crystal or external clock frequency must be equal to 32 times the data
rate.
Phase Detector Gain—Read/write binary field specifies one of four gain settings for the tim-
ing-recovery phase detector function.
Freeze PLL—Read/write control bit. When set, this bit zeros the proportional term of the loop
compensation filter and disables accumulator updates causing the PLL to hold its current fre-
quency. When cleared, proportional term effects and accumulator updates are enabled allowing
the PLL to track the phase of the incoming data.
PLL Gain—Read/write binary field specifies the gain (proportional and integral coefficients)
of the loop compensation filter.
6
pll_gain[1:0]
phase_detector_gain[1,0]
00
01
10
11
negate_symbol
clk_freq[1,0]
5
00
01
10
11
00
01
10
11
phase_detector_
gain[1]
Proportional Coefficients
4
N8960DSB
Normalized
phase_detector_
16
64
1
4
gain[0]
3
freeze_pll
2
Range Data Rate
Above 352 kbps
160 to 221 kbps
221 to 252kbps
Normalized Gain
Reserved
Single-Chip 2B1Q Transceiver
Reserved
Integral Coefficients
1
2
4
pll_gain[1]
Normalized
1
4096
256
32
1
pll_gain[0]
Bt8960
0