bt8960 Mindspeed Technologies, bt8960 Datasheet - Page 69

• Manufacturer Part Number: bt8960
• Description: Bt8960, Single-chip 2b1q Transceiver
• Manufacturer: Mindspeed Technologies

Bt8960
3.0 Registers
3.1 Conventions
Single-Chip 2B1Q Transceiver
3.2.33 0x2A, 0x2B—Noise-Level Histogram Threshold Register
(noise_histogram_th_low, noise_histogram_th_high)
Two-byte read/write register interpreted as a 16-bit, 2’s-complement number. The range of meaningful values is
limited to positive integers between 0x0000 and 0x7FFF. The value of this register is compared to the absolute
value of the slicer error signal produced by the detector. A count of error samples that exceed this threshold
(greater than) is accumulated in the noise-level histogram meter.
3.2.34 0x2C, 0x2D—Error Predictor Pause Threshold Register (ep_pause_th_low,
ep_pause_th_high)
Two-byte read/write register interpreted as a 16-bit, 2’s-complement number. The range of meaningful values is
limited to positive integers between 0x0000 and 0x7FFF. The value of this register is compared to the absolute
value of the slicer error signal produced by the detector. The result of this comparison (slicer error greater than
this threshold) is used to initiate a pause condition by zeroing the output of the error predictor correction signal
before subtraction from the receive signal path. Error predictor coefficient updates are not affected. The pause
condition lasts for a fixed 5-symbol period from the time the threshold was last exceeded.
3.2.35 0x2E—Scrambler Synchronization Threshold Register (scr_sync_th)
A 7-bit read/write register representing an unsigned binary number. The contents of this register are used to test
for scrambler synchronization during the automatic-scrambler synchronization mode of the symbol detector.
The test passes when the count of equivalent scrambler and detector output bits exceeds (greater than) the value
of this register. When the auto-scrambler sync mode is not enabled, the contents of this register are not used.
7
6
5
4
3
2
1
0
–
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
3.2.36 0x30, 0x31—Far-End High Alarm Threshold Register
(far_end_high_alarm_th_low, far_end_high_alarm_th_high)
A 2-byte read/write register interpreted as a 16-bit, 2’s-complement number. The range of meaningful values is
limited to positive integers between 0x0000 and 0x7FFF. The value of this register is compared to the value of
the far-end level meter. If the meter reading exceeds (greater than) this threshold, the high_felm interrupt flag is
set in the IRQ Source Register [irq_source; 0x05].
3.2.37 0x32, 0x33—Far-End Low Alarm Threshold Register
(far_end_low_alarm_th_low, far_end_low_alarm_th_high)
A 2-byte read/write register interpreted as a 16-bit, 2’s-complement number. The range of meaningful values is
limited to positive integers between 0x0000 and 0x7FFF. The value of this register is compared to the value of
the far-end level meter. If the meter reading exceeds (less than) this threshold, the low_felm interrupt flag is set
in the IRQ Source Register [irq_source; 0x05].
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N8960DSB