bt8960 Mindspeed Technologies, bt8960 Datasheet - Page 71

• Manufacturer Part Number: bt8960
• Description: Bt8960, Single-chip 2b1q Transceiver
• Manufacturer: Mindspeed Technologies

Bt8960
Single-Chip 2B1Q Transceiver
3.2.41 0x3A—Symbol Detector Modes Register (detector_modes)
enable_peak_
detector
output_mux_
control[1,0]
scr_out_to_dfe
two_level
lfsr_lock
enable_peak_det
ector
7
output_mux_con
Enable Peak Detector—Read/write control bit that enables the peak detection function when
set; disables the function when cleared. When enabled, the peak detector output overrides the
slicer output if the peak detection criteria are met. If the criteria are not met, or if the function
is disabled, the slicer output is used and peak detector output is ignored.
Output Multiplexer Control—Read/write binary field that selects the source of the detector
output connected to the channel unit receive interface.
Scrambler Output to DFE—Read/write control bit that selects the source of the detector output
connected to the DFE and timing recovery module inputs, and the transmitter’s detector loop-
back input. When set, this bit selects the scrambler/descrambler function; when cleared, it
selects the slicer/peak detector output.
Two-Level Mode—Read/write control bit that selects two-level mode when set, four-level
mode when cleared. Affects the slicer and the scrambler/descrambler function. In two-level
mode, the slicer uses a single threshold set at zero to recover sign bits only; all magnitude
information is lost. Scrambler/descrambler updates are slowed to the symbol rate (half the nor-
mal bit rate) to process only sign information as well; all magnitude output bits are sourced
with a constant logic zero value producing two-level symbols constrained to +3 and –3 values.
[cursor_level_low, cursor_level_high; 0x36–0x37], as well as the zero threshold, to recover
both sign and magnitude information. The scrambler/descrambler is updated at the full bit rate
to process both sign and magnitude bits as well.
LFSR Lock—Read/write control bit that enables the auto scrambler synchronization mode
(lfsr_lock) in the detector when set; disables this mode when cleared. Affects the behavior of
the scrambler/descrambler function, overriding the descr_on setting. When enabled, the
scrambler/descrambler is forced into the descrambler mode for 23 cycles. It is then switched to
the scrambled-ones mode for 128 cycles. While in this mode, the outputs of the scrambler and
the slicer/peak detector are compared against one another. The number of equivalent bits
(equal comparisons) is accumulated and compared to the value of the scrambler synchroniza-
tion threshold register [scr_sync_th; 0x2E].
interrupt flag is set in the IRQ Source Register [irq_source; 0x05] and the process terminates
with the scrambler/descrambler left in the scrambled-ones mode. (The sync interrupt flag can-
trol[1]
In 4-level mode, the slicer uses two thresholds derived from the Cursor Level Register
At any time during the 128 cycles, if the count exceeds the threshold (greater than), the sync
6
output_mux_control[1,0]
output_mux_con
trol[0]
5
00
01
10
11
scr_out_to_dfe
4
N8960DSB
two_level
Same as scr_out_to_dfe selection.
Transmitter loopback output from CU transmit interface.
Scrambler/descrambler output.
Reserved.
3
Detector Output to CU Receive Interface
lfsr_lock
2
htur_lfsr
1
3.1 Conventions
3.0 Registers
descr_on
0
61