bt8960 Mindspeed Technologies, bt8960 Datasheet - Page 47

• Manufacturer Part Number: bt8960
• Description: Bt8960, Single-chip 2b1q Transceiver
• Manufacturer: Mindspeed Technologies

3.1 Conventions
Unless otherwise noted, the following conventions apply to all applicable register descriptions:
• For storage of multiple-bit data fields within a single byte-wide register, the Least Significant Bits
• If only a single data field is stored in a byte-wide register, the field will be justified such that the LSB of
• For storage of multiple-byte data words across multiple byte-wide registers, the least significant bytes
• When writing to any control or data register with less than all 8-bit positions defined, a logic zero value
• When reading from any control/status or data register with less than all 8-bit positions defined, an inde-
• Register values are not affected by RST pin assertion, except for the mode bit of the Global Modes and
• The initial values of all registers and RAM are undefined after power is applied. Exceptions include the
• The register and bit mnemonics used here are based on the mnemonics used in the Rockwell bit pump
(LSBs) of the field are located at the lower register-bit positions, while the Most Significant Bits
(MSBs) are located at the higher positions.
the field is located in the lowest register-bit position, bit 0.
of the word are located at the lower byte-address locations, while the most significant bytes are located
at the higher byte-address locations.
must be assigned to each unused/undefined/reserved position. Writing a logic one value to any of these
positions may cause undefined behavior.
terminate value will be returned from each unused/undefined/reserved position.
Status Register [global_modes; 0x00], the hclk_freq[1,0] field of the Serial Monitor Source Select Reg-
ister [serial_monitor_source; 0x01] and the clk_freq[1,0] field of the PLL Modes Register [pll_modes;
0x22]. Upon RST pin assertion, all RAM is lost except for the equalizer microcode and scratch pad
RAM.
mode bit of the Global Modes and Status Register, the hclk_freq[1,0] field of the Serial Monitor Source
Select Register and the clk_freq[1,0] field of the PLL Modes Register. In addition, the JTAG state is
reset when power is applied.
software.
3.0 Registers
N8960DSB
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