bt8960 Mindspeed Technologies, bt8960 Datasheet - Page 29

• Manufacturer Part Number: bt8960
• Description: Bt8960, Single-chip 2b1q Transceiver
• Manufacturer: Mindspeed Technologies

Bt8960
Single-Chip 2B1Q Transceiver
2.2.1 Variable Gain Amplifier
Figure 2-2. First-Order Echo Cancellation Using the Variable Gain Amplifier
(Twisted Pair)
Line
Transformer
Line
+
–
2.2 Receive Section
Like the transmit section, the receive section consists of both analog and digital
circuitry. The VGA provides the interface to the analog signals received from the
line and the hybrid. The Analog-to-Digital Converter (ADC) then digitizes the
analog signal so it can be further processed in the digital signal Processing (DSP)
section of the receiver. The receiver DSP section includes: front-end processing,
echo cancellation, equalization, and symbol detection.
The Variable Gain Amplifier (VGA) has two purposes. The first is to provide a
dual-differential analog input so the pseudo-transmit signal created by the hybrid
can be subtracted from the signal from the line transformer. This subtraction pro-
vides first-order echo cancellation, which results in a first-order approximation of
the signal received from the line. Figure 2-1 illustrates the recommended sug-
gested echo-cancellation circuit interconnections. All off-chip circuitry, including
the hybrid and anti-alias filters, consists entirely of passive components. Further
echo cancellation occurs in the receiver DSP.
received signal prior to passing it to the ADC. This reduces the resolution
required for the ADC. There are six gain settings ranging from 0 dB to 15 dB. The
gain is controlled via the gain[2:0] control bits in the ADC Control Register
[adc_control; 0x21]. See the Registers section of this datasheet for a more
detailed description of the gain[2:0] control bits.
Impedance
Resistors
Matching
The second purpose of the VGA is to provide programmable gain of the
Line
+
–
Hybrid
N8960DSB
Off-Chip Circuitry
Anti-Alias
Anti-alias
Filter
Filter
On-Chip Circuitry
RXBN
RXBP
RXP
RXN
TXP
TXN
+
+
–
–
+
–
Driver
Line
2.0 Functional Description
+
2.2 Receive Section
–
Gain[2:0]
To
ADC
19