tmp89fm82 TOSHIBA Semiconductor CORPORATION, tmp89fm82 Datasheet - Page 94

• Manufacturer Part Number: tmp89fm82
• Description: 8 Bit Microcontroller Tlcs-870/c1 Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

5.3
Functions
RA000
5.3
5.3.1
5.3.2
and detecting releasing of the 8-bit up counter outside the clear time.
counter at random times and comparing the value to the last read value.
Functions
The watchdog timer can detect the CPU malfunctions and deadlock by detecting the overflow of the 8-bit up counter
The watchdog timer stoppage and other abnormalities can be detected by reading the count value of the 8-bit up
Watchdog timer
source clock
8-bit up counter value
WDCTR<WDTEN>
WDCTR<WDTEN>
Interrupt request signal
counting the source clock.
that the watchdog timer is enabled.
Disabling the watchdog timer operation clears the 8-bit up counter to "0".
code into WDCDR.
8-bit up counter can be cleared at any time.
of the 8-bit up counter. If the operation for releasing the 8-bit up counter is attempted outside the clear time, a
watchdog timer interrupt request signal occurs.
within the clear time, a watchdog timer reset request signal or a watchdog timer interrupt request signal occurs
due to the overflow, depending on the WDCTR<WDTOUT> setting.
Setting of enabling/disabling the watchdog timer operation
Setting the clear time of the 8-bit up counter
Setting WDCTR<WDTEN> to "1" enables the watchdog timer operation, and the 8-bit up counter starts
WDCTR<WDTEN> is initialized to "1" after the warm-up operation that follows reset is released. This means
To disable the watchdog timer operation, clear WDCTR<WDTEN> to "0" and write 0xB1 into WDCDR.
To re-enable the watchdog timer operation, set WDCTR<WDTEN> to "1". There is no need to write a control
WDCTR<WDTW> sets the clear time of the 8-bit up counter.
When WDCTR<WDTW> is "00", the clear time is equal to the overflow time of the 8-bit up counter, and the
When WDCTR<WDTW> is not "00", the clear time is fixed to only a certain period within the overflow time
At this time, the watchdog timer is not cleared but continues counting. If the 8-bit up counter is not cleared
Note:If the overflow of the 8-bit up counter occurs at the same time as 0xB1 (disable code) is written into
Note:The 8-bit up counter source clock operates out of synchronization with WDCTR<WDTEN>. Therefore,
Figure 5-2 WDCTR<WDTEN> Set Timing and Overflow Time
WDCDR with WDCTR<WDTEN> set at "1", the watchdog timer operation is disabled preferentially and
the overflow detection is not executed.
the first overflow time of the 8-bit up counter after WDCTR<WDTEN> is set to "1" may get shorter by a
maximum of 1 source clock. The 8-bit up counter must be cleared within the period of the overflow time
minus 1 source clock cycle.
1 clock (max.)
0x00
Page 78
Overflow time
0x01
Overflow time
0xFF
0x00
TMP89FM82