tmp89fm82 TOSHIBA Semiconductor CORPORATION, tmp89fm82 Datasheet - Page 302

• Manufacturer Part Number: tmp89fm82
• Description: 8 Bit Microcontroller Tlcs-870/c1 Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

19.3
Position Detection Unit
RA000
19.3.1
fcgck
Position signal input
Sampling
control
circuit
Configuration of the position detection unit
2
1
Prescaler
・ The position detection unit is controlled by the Position Detection Control Register (PDCRA, PDCRB).
・ When unmatch detect mode is selected for position detection, the unit stores the sampled status of the
・ In unmatch detect mode, the port status at sampling start can be read by (PDCRC<PDTCT>) .
・ When starting and stopping position detection synchronously with the timer, position detection is started
・ Three sampling mode can be selected by (PDCRB<SPLMD>) 2bit : mode where sampling is performed
・ In case of sampling mode while the lower phases turn on current, sampling is performed for a period
2
2
PDU
PDV
PDW
2
3
2
After the position detect function is enabled, the unit starts sampling the position detect port triggered
by Timer 2 or in software. For the case of ordinary mode, when the status of the position detect input
port matches the expected value (MDOUT<PDEXP> of the PMD Output Register, the unit generates
a position detect interrupt and finishes sampling, waiting for start of the next sampling.
position detect port in memory at the time it started sampling. When the port input status changes from
that of sampling start, an interrupt is generated.
by Timer 2 and position detection is stopped by Timer 3.
only while PWM is on, mode where sensors such as Hall elements are sampled regularly, and mode
where sampling is performed while the lower side turn on current (when performing sampling only
while PWM is on, 3 phase DUTY must be set for all three phases in common).
from when the set sampling delay time has elapsed after the lower side turn on current till when the
current application is turned off. Sampling is performed independently at each phase, and the sampling
result is retained while sampling is off. If while sampling at some phase is off, the input and the expected
value at other phase being sampled match, position is detected and an positon detect interrupt is gen-
erated.
4
Figure 19-4 Configuration of the Position Detection Circuit
fcgck/2
fcgck/2
fcgck/2
fcgck/2
Clock selector
PDNUM
2
Latch
4
3
2
1
Sampling delay set register
PMD output register
-
7, 6, 5, 4, 3, 2, 1, 0
14, 13, 12
MDOUT
Buffer
SDREG
Delay
circuit
-
-
-
-
Position signal expected value
Coincidence detection
Sampling
control
Page 286
4
Erroneous detection prevention circuit
Position detection control register
7, 6
Reset control
Counter
5, 4
PDCRB
3, 2, 1, 0
MDOUTsync
7, 6, 5, 4
PDCRA
3
2
1
2
0
Position
detection
interrupt
INTPDC
Timer interrupt
INTTMR2/3
TMP89FM82
PWMON