tmp89fm82 TOSHIBA Semiconductor CORPORATION, tmp89fm82 Datasheet - Page 280

• Manufacturer Part Number: tmp89fm82
• Description: 8 Bit Microcontroller Tlcs-870/c1 Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

17.2
SEI Registers
RA000
17.2
Read-modify-write instruction are prohibited.
17.2.1
(0F7AH)
SECR
which are used to set up the SEI system and enable/disable SEI operation.
17.2.1.1
The SEI interface has the SEI Control Register (SECR), SEI Status Register (SESR), and SEI Data Register (SEDR)
Note 1: If mode fault detection is enabled, an interrupt is generated when the MODF flag (SESR<MODF>) is set.
Note 2: SEI operation can only be disabled after transfer is completed. Before the SEI can be used, Control register of general-
Note 3: Master/slave settings must be made before enabling SEI operation (This means that the SECR<MSTR> bit must first be
SEI Registers
SEI Control Register (SECR)
MODE
purpose port used combinedly must be set for the SEI function (In case of P2 port, P2CR and P2FC ).
When using the SEI as the master, set the SECR<MSTR>bit tp "1" and the SECR<SEE> bit to “1” (to enable SEI operation)
and then place transmit data in the SEDR register. This initiates transmission/reception.
set before setting the SECR<SEE> bit to “1”).
(1)
MODE
MSTR
CPOL
CPHA
7
SEE
BOS
SER
Transfer rate
the SEI is operating as the master.
The table below shows the relationship between settings of the SER bit and transfer bit rates when
Master mode (Transfer rate = fcgck/Internal clock divide ratio (unit: bps))
SEE
6
Table 17-1 SEI Transfer Rate
Mode fault detection (Note1)
SEI operation (Note2)
Bit order selection
Mode selection (Note3)
Clock polarity
Clock phase
Selects SEI transfer rate
SER
00
01
10
11
BOS
5
Internal Clock Divide Ratio of SEI
MSTR
4
32
2
4
8
CPOL
3
Page 264
0: Enables mode fault detection
1: Disables mode fault detection
It is available in Master mode only.
(Note: Make sure to set <MODE> bit to "1" for disabling Mode fault de-
tection
0: Disables SEI operation
1: Enables SEI operation
0: Transmitted beginning with the MSB (bit 7) of SEDR register
1: Transmitted beginning with the LSB (bit 0) of SEDR register
0: Sets SEI for slave
1: Sets SEI for master
0: Selects active-“H” clock. SECLK remains “L” when IDLE.
1: Selects active-“L” clock. SECLK remains “H” when IDLE.
Selects clock phase. For details, refer to "17.5 SEI Transfer Formats "
00: Divide-by-2
01: Divide-by-4
10: Divide-by-8
11: Divide-by-32
CPHA
2
Transfer Rate when fc = 8 MHz
1
SER
250 kbps
4 Mbps
2 Mbps
1 Mbps
0
(Initial value: 0000 0100)
TMP89FM82
R/W