tmp89fm82 TOSHIBA Semiconductor CORPORATION, tmp89fm82 Datasheet - Page 310

• Manufacturer Part Number: tmp89fm82
• Description: 8 Bit Microcontroller Tlcs-870/c1 Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

19.4
Timer Unit
RA000
MTCRB
MTCRA
7, 6, 5
7
5
3
2
1
4
3
2
1
0
19.4.1.1
MCAP
CMP1
CMP2
CMP3
SWRES
DBOUT
PDCCP
RBPDC
RBTM3
SWCP
TMOF
TMCK
TMEN
CLCP
RBCL
Timer Circuit Register Functions
Mode capture
Timer 1 (commutation)
Timer 2 (position detection start)
Timer 3 (overflow)
(commutation)
(position detection start)
detection interrupt
Debug output (P67, P77)
imer 1 interrupt
imer 2 interrupt
imer 3 interrupt or position
Debug output
Mode timer overflow
Capture mode timer by over-
load protection
Capture mode timer in soft-
ware
Capture mode timer by posi-
tion detection
Select clock
Reset mode timer from Timer
3
Reset mode timer by overload
protection
Reset mode timer in software
Reset mode timer by position
detection
Enable/disable mode timer
Figure 19-8 DBOUT Debug Output Diagram
Debug output can be produced by setting this bit to 1. Because interrupt signals to the
interrupt control circuit are used for each interrupt, hardware debugging without software
delays are possible. See the debug output diagram (Figure 19-8). Output ports: P80.
This bit shows that the timer has overflowed.
When this bit is set to "1", the timer value can be captured using the overload protection
signal (CL) as a trigger.
When this bit is set to "1", the timer value can be captured in software (e.g., by writing to
this register).
When this bit is set to "1", the timer value can be captured using the position detection
signal as a trigger.
Select the timer clock.
When this bit is set to "1", the mode timer is reset by a trigger from Timer 3.
When this bit is set to "1", the mode timer is reset by the overload protection signal (CL) as
a trigger.
When this bit is set to "1", the mode timer is reset in software (e.g., by writing to this regis
er)
When this bit is set to "1", the mode timer is reset by the position detection signal as a trig
er.
The mode timer is started by setting this bit to "1". Therefore, Timers 1 to 3 must be set
with CMP before setting this bit. If this bit is set to 0 after setting CMP, CMP settings become
ineffective.
Position detection interval can be read out.
Timers 1 to 3 are enabled while the mode timer is operating. An interrupt can be generated
once by setting the corresponding bit in this register. The interrupt is disable when an in-
terrupt is generated or the timer is reset. To use the timer again, set the register back again
even if data is same.
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