tmp89fm82 TOSHIBA Semiconductor CORPORATION, tmp89fm82 Datasheet - Page 285

• Manufacturer Part Number: tmp89fm82
• Description: 8 Bit Microcontroller Tlcs-870/c1 Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

RA000
17.5
17.5.1
be selected between two.
The transfer formats are set using CPHA and CPOL (SECR<CPHA,CPOL>). CPHA allows transfer protocols to
SEI Transfer Formats
Figure 17-2 shows a transfer format when CPHA = 0.
Table 17-4 Transfer Format Details when CPHA = 0
CPHA (SECR register bit 2) = 0 format
・ Master mode.
・ Slave mode
SECLK Cycle
SECLK
(CPOL = 0)
SECLK
(CPOL = 1)
MOSI
MISO
SS
SEF
CPOL = 0
CPOL = 1
data changes state on the MOSI pin a half clock period before the shift clock starts pulsing. Use BOS
(SECR<BOS>) to select whether the data should be shifted out beginning with the MSB or LSB. The
SEF flag (SESR<SEF>) is set after the last shift cycle.
completion of transfer and the SS pin goes “H” again. Do not write the next data to the SEDR register
while SS pin is “L”. A write during this period causes collision of writes, so that the WCOL flag
(SESR<WCOL>) is set. .
In master mode, transfer is initiated by writing new data to the SEDR register. At this time, the new
Before writing data to the SEDR (SEI Data Register), it is needed to confirm the SEF flag set upon
Internal
Shift clock
Figure 17-2 Transfer Format When CPHA = 0
SECLK Level when not
Communicating (IDLE)
“H” level
“L” level
1
2
Falling edge of transfer clock
Rising edge of transfer clock
Page 269
3
Data Shift
4
5
6
Rising edge of transfer clock
Falling edge of transfer clock
7
Data Sampling
8
TMP89FM82