tmp89fm82 TOSHIBA Semiconductor CORPORATION, tmp89fm82 Datasheet - Page 351

• Manufacturer Part Number: tmp89fm82
• Description: 8 Bit Microcontroller Tlcs-870/c1 Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

RA000
20.3.3
ADCCR1<AMD>
ADCCR1<ADRS>
Conversion
operation
Status of ADCDRL
and ADCDRH
ADCCR2<EOCF>
INTADC interrupt
Read of ADCDRH
Read of ADCDRL
conversion. After the AD conversion is finished, the conversion result is stored in the AD converted value register
(ADCDRL and ADCDRH), ADCCR2<EOCF> is set to "1", and the AD conversion finished interrupt (INTADC)
is generated. The AD converted value registers (ADCDRL and ADCDRH) should be usually read according to
the INTADC interrupt processing routine. If the upper side (ADCDRH) of the AD converted value register is
read, ADCCR2<EOCF> is cleared to "0".
the start of AD conversion, ADCCR1<ADRS> is automatically cleared. After the first AD conversion is finished,
the conversion result is stored in the AD converted value registers (ADCDRL and ADCDRH), ADCCR2<EOCF>
is set to "1", and the AD conversion finished interrupt (INTADC) is generated. After this interrupt is generated,
the second (next) AD conversion starts immediately.
finished. If the next AD conversion is finished in the interim between a read of ADCDRL and a read of ADCDRH,
the previous converted value is retained without overwriting the AD converted value registers (ADCDRL and
ADCDRH). In this case, the INTADC interrupt request is not generated, and the conversion result is lost. (See
Figure 20-3.)
ADCCR1<AMD>, AD conversion stops immediately. In this case, the converted value is not stored in the AD
converted value register. As AD conversion starts, ADCCR2<ADBF> is set to "1". It is cleared to "0" if "00" is
written to AMD.
In repeat mode, the voltage at an analog input pin designated at ADCCR1<SAIN> is AD converted repeatedly.
Setting ADCCR1<ADRS> to "1" after setting ADCCR1<AMD> to "11" allows AD conversion to start. After
The AD converted value registers (ADCDRL and ADDRH) should be read before the next AD conversion is
To stop AD conversion, write "00" (AD operation disable) to ADCCR1<AMD>. As "00" is written to
Repeat mode
The INTADC interrupt request is
Note:Do not perform the following operations on the ADCCR1 register when AD conversion is being executed
between a read of ADCDRL
not generated in the interim
(ADCCR2<ADBF>="1"). If the following operations are performed, there is the possibility that AD con-
version may not be executed properly.
・ Changing the ADCCR1<SAIN> setting
・ Setting ADCCR1<AINEN> to "0"
・ Changing the ADCCR1<AMD> setting (except a forced stop by setting AMD to "00")
・ Setting ADCCR1<ADRS> to "1"
and a read of ADCDRH.
Indeterminate
AD conversion start
Figure 20-3 Repeat Mode
2nd conversion
Result of the 1st conversion
Read of
conversion
result
Result of the
“11”
Page 335
Result of the 3rd
Read of
conversion
result
conversion
Read of
conversion
result
Result of the 3rd
Result of the 4th
conversion
conversion
Read of
conversion
result
Result of the 4th
Read of
conversion
result
AD conversion is
suspended.
The conversion result
is not stored.
conversion
“00”
Read of
conversion
result
A read of the
conversion result
will clear EOCF.
TMP89FM82