tmp89fm82 TOSHIBA Semiconductor CORPORATION, tmp89fm82 Datasheet - Page 61

• Manufacturer Part Number: tmp89fm82
• Description: 8 Bit Microcontroller Tlcs-870/c1 Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

RA000
2.4.4
2.4.4.1
2.4.4.2
Reset Signal Generating Factors
Reset signals are generated by each factor as follows:
release voltage. When the supply voltage rises above the power-on reset release voltage, the power-on reset
signal is released.
on reset detection voltage.
The power-on reset is an internal reset that occurs when power is turned on.
During power-up, a power-on reset signal is generated while the supply voltage is below the power-on reset
During power-down, a power-on reset signal is generated when the supply voltage falls below the power-
Refer to "Power-on Reset circuit".
This is an external reset that is generated by the RESET pin input.
Power-on reset
External reset input (RESET pin input)
・ During power-up
-
-
When the supply voltage rises rapidly
reset can be released by a power-on reset or an external reset (RESET pin input).
that the TMP89FM82 is reset when either or both of these reset sources are asserted.
the RESET pin level changes from Low to High before the supply voltage rises above the
power-on-reset release voltage (V
ginning), the reset time depends on the power-on reset. If the RESET pin level changes from
Low to High after the supply voltage rises above V
external reset.
In the latter case, a warm-up period begins when the RESET pin level becomes High. Upon
completion of the warm-up period, the CPU and peripheral circuits start operating (Figure
2-17).
When the supply voltage rises slowly
by using the RESET pin. In this case, hold the RESET pin Low until the supply voltage rises
to the operating voltage range and oscillation is stabilized. When this state is achieved, wait
at least 5 [μs] and then pull the RESET pin High. Changing the RESET pin level to High
starts a warm-up period. Upon completion of the warm-up period, the CPU and peripheral
circuits start operating (Figure 2-17).
When the power supply rise time (t
The power-on reset logic and external reset (RESET pin input) logic are ORed. This means
Therefore, the reset time is determined by the reset source with a longer reset period. If
In the former case, a warm-up period begins when the power-on reset signal is released.
When the power supply rise time (t
Page 45
PROFF
VDD
VDD
) (or if the RESET pin level is High from the be-
) is longer than 5 [ms], the reset must be released
) is shorter than 5 [ms] with enough margin, the
PROFF
, the reset time depends on the
TMP89FM82