mpc5644a Freescale Semiconductor, Inc, mpc5644a Datasheet - Page 99

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mpc5644a

Manufacturer Part Number
mpc5644a
Description
Mpc5644a Microcontroller Data Sheet
Manufacturer
Freescale Semiconductor, Inc
Datasheet
3.13
Use the SWSC field in the ECSM_MUDCR register to specify an additional wait state for the device SRAM. By default, no
wait state is added.
Please see the “MPC5644A Microcontroller Reference Manual” for details.
3.14
Freescale Semiconductor
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Stop mode recovery time is the time from the setting of either of the enable bits in the ADC Control Register to the
time that the ADC is ready to perform conversions.Delay from power up to full accuracy = 8 ms.
At V
Below disruptive current conditions, the channel being stressed has conversion values of 0x3FF for analog inputs
greater then V
Exceeding limit may cause conversion error on stressed channels and on unstressed channels. Transitions within
the limit do not affect device reliability or cause permanent damage.
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,
calculate resistance values using V
calculated values.
Condition applies to two adjacent pins at injection limits.
Performance expected with production silicon.
All channels have same 10 k < Rs < 100 k; Channel under test has Rs=10 k; I
Applies only to differential channels.
Variable gain is controlled by setting the PRE_GAIN bits in the ADC_ACR1-8 registers to select a gain factor of 1,
2, or 4. Settings are for differential input only. Tested at 1 gain. Values for other settings are guaranteed by as
indicated.
At V
Guaranteed 10-bit mono tonicity.
Configuring SRAM wait states
Platform flash controller electrical characteristics
RH
RH
– V
– V
RL
RL
= 5.12 V, one count = 1.25 mV without using pregain.
= 5.12 V, one LSB = 1.25 mV.
RH
Table 29. APC, RWSC, WWSC settings vs. frequency of operation
Max. Flash Operating
Maximum Operating Frequency
Frequency (MHz)
and 0x0 for values less then V
Table 28. Cutoff frequency for additional SRAM wait state
153 MHz
120 MHz
30 MHz
60 MHz
90 MHz
TBD
TBD
Preliminary—Subject to Change Without Notice
4
MPC5644A Microcontroller Data Sheet, Rev. 4
TBD
TBD
POSCLAMP
= V
0b000
0b001
0b010
0b011
0b100
0b101
0b110
APC
RL
DDA
. Other channels are not affected by non-disruptive conditions.
3
+ 0.5 V and V
RWSC
0b000
0b001
0b010
0b011
0b100
0b101
0b110
NEGCLAMP
SWSC Value
3
0
1
= – 0.3 V, then use the larger of the
INJ
WWSC
=I
TBD
TBD
TBD
TBD
TBD
TBD
TBD
INJMAX
Electrical characteristics
1,2
,I
INJMIN
99

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