mpc5644a Freescale Semiconductor, Inc, mpc5644a Datasheet - Page 3

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mpc5644a

Manufacturer Part Number
mpc5644a
Description
Mpc5644a Microcontroller Data Sheet
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1
This document provides electrical specifications, pin assignments, and package diagrams for the MPC5644A series of
microcontroller units (MCUs). For functional characteristics, refer to the MPC5644A Microcontroller Reference Manual.
The microcontroller’s e200z4 host processor core is built on Power Architecture
embedded applications. In addition to the Power Architecture technology, this core supports instructions for digital signal
processing (DSP).
The MPC5644A has two levels of memory hierarchy consisting of 8 KB of instruction cache, backed by 192 KB on-chip SRAM
and 4 MB of internal flash memory. The MPC5644A includes an external bus interface, and also a calibration bus that is only
accessible when using the Freescale VertiCal Calibration System.
This document describes the features of the MPC5644A and highlights important electrical and physical characteristics of the
device.
1.1
Table 1
Freescale Semiconductor
summarizes the MPC5644A and compares it to the MPC5634M.
Overview
Device comparison
Process
Core
Windowing software watchdog
Core Nexus
SRAM
Flash
Flash fetch accelerator
External bus
Calibration bus
DMA
DMA Nexus
Serial
SIMD
VLE
Cache
Non-Maskable Interrupt (NMI)
MMU
MPU
Crossbar switch
Core performance
Feature
Preliminary—Subject to Change Without Notice
MPC5644A Microcontroller Data Sheet, Rev. 4
Table 1. MPC5644A device comparison
16-bit (incl 32-bit muxed)
16-bit (incl 32-bit muxed)
8 KB instruction
MPC5644A
0–150 MHz
4  256-bit
Class 3+
24 entry
16 entry
e200z4
192 KB
90 nm
64 ch.
4 MB
5  4
3
NMI & Critical Interrupt
®
None
technology and designed specifically for
Yes
Yes
Yes
MPC5634M
4  128-bit
0–80 MHz
Class 2+
16 entry
e200z3
1.5 MB
90 nm
94 KB
32 ch.
16-bit
None
3  4
No
No
2
Overview
3

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