mpc5644a Freescale Semiconductor, Inc, mpc5644a Datasheet - Page 65

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mpc5644a

Manufacturer Part Number
mpc5644a
Description
Mpc5644a Microcontroller Data Sheet
Manufacturer
Freescale Semiconductor, Inc
Datasheet
RD_WR
TA
TS
WE[2:3]
WE[0:3]/BE[0:3]
eMIOS[0:23]
AN[0:39]
FCK
MA[0:2]
REFBYPC
SDI
SDO
SDS
VRH
VRL
SCI_A_RX
SCI_B_RX
SCI_C_RX
Signal
EBI
EBI
EBI
EBI
EBI
eMIOS
eQADC
eQADC
eQADC
eQADC
eQADC
eQADC
eQADC
eQADC
eQADC
eSCI_A - eSCI_C
Module or Function
Table 5. Signal details (continued)
RD_WR indicates whether the current transaction is a read
access or a write access.
TA is asserted to indicate that the slave has received the data
(and completed the access) for a write cycle, or returned data for
a read cycle. If the transaction is a burst read, TA is asserted for
each one of the transaction beats. For write transactions, TA is
only asserted once at access completion, even if more than one
write data beat is transferred.
The Transfer Start signal (TS) is asserted by the MPC5644A to
indicate the start of a transfer.
Write enables are used to enable program operations to a
particular memory. WE[2:3] are only asserted for write accesses
Write enables are used to enable program operations to a
particular memory. These signals can also be used as byte
enables for read and write operation by setting the WEBS bit in
the appropriate EBI Base Register (EBI_BRn). WE[0:3] are only
asserted for write accesses. BE[0:3] are asserted for both read
and write accesses
eMIOS I/O channels
Single-ended analog inputs for analog-to-digital converter
eQADC free running clock for eQADC SSI.
These three control bits are output to enable the selection for an
external Analog Mux for expansion channels.
Bypass capacitor input
Serial data in
Serial data out
Serial data select
Voltage reference high input
Voltage reference low input
eSCI receive
Description

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