mpc5644a Freescale Semiconductor, Inc, mpc5644a Datasheet - Page 18

• Manufacturer Part Number: mpc5644a
• Description: Mpc5644a Microcontroller Data Sheet
• Manufacturer: Freescale Semiconductor, Inc

Overview
1.2.20
The CRC computing unit is dedicated to the computation of CRC off-loading the CPU. The CRC features:
1.2.21
The ECSM provides a myriad of miscellaneous control functions regarding program-visible information about the platform
configuration and revision levels, a reset status register, a software watchdog timer, wakeup control for exiting sleep modes,
and information on platform memory errors reported by error-correcting codes and/or generic access error information for
certain processor cores.
The Error Correction Status Module supports a number of miscellaneous control functions for the platform. The ECSM includes
these features:
The sources of the ECC errors are:
1.2.22
The MPC5644A device features an external bus interface that is available in 324 TEPBGA and calibration packages.
The EBI supports operation at frequencies of system clock /1, /2 and /4, with a maximum frequency support of 80 MHz.
Customers running the device at 120 MHz or 132 MHz will use the /2 divider, giving an EBI frequency of 60 MHz or 66 MHz.
Customers running the device at 80 MHz will be able to use the /1 divider to have the EBI run at the full 80 MHz frequency.
Features include:
18
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Optional programmable watchdog window mode
Can optionally cause system reset or interrupt request on timeout
Reset by writing a software key to memory mapped register
Enabled out of reset
Configuration is protected by a software key or a write-once register
Support for CRC-16-CCITT (x25 protocol):
— X
Support for CRC-32 (Ethernet protocol):
— X
Zero wait states for each write/read operations to the CRC_CFG and CRC_INP registers at the maximum frequency
Registers for capturing information on platform memory errors if error-correcting codes (ECC) are implemented
For test purposes, optional registers to specify the generation of double-bit memory errors are enabled on the
MPC5644A.
Flash
SRAM
Peripheral RAM (FlexRay, CAN, eTPU2 Parameter RAM)
1.8 V to 3.3 V ± 10% I/O (1.6 V to 3.6 V)
Memory controller with support for various memory types
16-bit data bus, up to 22-bit address bus
Pin muxing included to support 32-bit muxed bus
Selectable drive strength
Configurable bus speed modes
Bus monitor
Configurable wait states
Cyclic redundancy check (CRC) module
Error correction status module (ECSM)
External bus interface (EBI)
16
32
+ X
+ X
12
26
+ X
+ X
5
23
+ 1
+ X
22
+ X
Preliminary—Subject to Change Without Notice
MPC5644A Microcontroller Data Sheet, Rev. 4
16
+ X
12
+ X
11
+ X
10
+ X
8
+ X
7
+ X
5
+ X
4
+ X
2
+ X + 1
Freescale Semiconductor