mpc5644a Freescale Semiconductor, Inc, mpc5644a Datasheet - Page 12

• Manufacturer Part Number: mpc5644a
• Description: Mpc5644a Microcontroller Data Sheet
• Manufacturer: Freescale Semiconductor, Inc

Overview
The eTPU2 includes these distinctive features:
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32 channels; each channel associated with one input and one output signal
— Enhanced input digital filters on the input pins for improved noise immunity
— Identical, orthogonal channels: each channel can perform any time function. Each time function can be assigned
— Each channel has an event mechanism which supports single and double action functionality in various
— Input and output signal states visible from the host
2 independent 24-bit time bases for channel synchronization:
— First time base clocked by system clock with programmable prescale division from 2 to 512 (in steps of 2), or by
— Second time base counter can work as a continuous angle counter, enabling angle based applications to match
— Both time bases can be exported to the eMIOS timer module
— Both time bases visible from the host
Event-triggered microengine:
— Fixed-length instruction execution in two-system-clock microcycle
— 14 KB of code memory (SCM)
— 3 KB of parameter (data) RAM (SPRAM)
— Parallel execution of data memory, ALU, channel control and flow control sub-instructions in selected
— 32-bit microengine registers and 24-bit wide ALU, with 1 microcycle addition and subtraction, absolute value,
— Additional 24-bit Multiply/MAC/Divide unit which supports all signed/unsigned Multiply/MAC combinations,
Resource sharing features support channel use of common channel registers, memory and microengine time:
— Hardware scheduler works as a “task management” unit, dispatching event service routines by predefined,
— Automatic channel context switch when a “task switch” occurs, that is, one function thread ends and another
— SPRAM shared between host CPU and eTPU2, supporting communication either between channels and host or
— Hardware implementation of four semaphores support coherent parameter sharing between both eTPU engines
— Dual-parameter coherency hardware support allows atomic access to two parameters by host
Test and development support features:
— Nexus Class 1 debug, supporting single-step execution, arbitrary microinstruction execution, hardware
— Software breakpoints
— SCM continuous signature-check built-in self test (MISC - multiple input signature calculator), runs concurrently
to more than one channel at a given time, so each signal can have any functionality.
combinations. It includes two 24-bit capture registers, two 24-bit match registers, 24-bit greater-equal and
equal-only comparators.
output of second time base prescaler
angle instead of time
combinations
bitwise logical operations on 24-bit, 16-bit, or byte operands, single-bit manipulation, shift operations, sign
extension and conditional execution
and unsigned 24-bit divide. The MAC/Divide unit works in parallel with the regular microcode commands.
host-configured priority
begins to service a request from other channel: channel-specific registers, flags and parameter base address are
automatically loaded for the next serviced channel
inter-channel
breakpoints and watchpoints on several conditions
with eTPU2 normal operation
Preliminary—Subject to Change Without Notice
MPC5644A Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor