mpc5644a Freescale Semiconductor, Inc, mpc5644a Datasheet - Page 106

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mpc5644a

Manufacturer Part Number
mpc5644a
Description
Mpc5644a Microcontroller Data Sheet
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Electrical characteristics
3.17.2
106
1
2
3
10
11
12
13
14
15
#
1
2
3
4
5
6
7
8
9
JTAG timing specified at V
Low-Swing mode, T
boundary scan only. See
Pad delay is 8–10 ns. Remainder includes TCK pad delay, clock tree delay logic delay and TDO output pad delay.
For 20 MHz TCK.
t
t
IEEE 1149.1 interface timing
TMSH,
TMSS,
t
t
TCKRISE
JCMPPW
t
t
t
t
t
t
t
TDOHZ
t
JCMPS
t
BSDVZ
BSDHZ
BSDST
BSDHT
t
JCYC
t
TDOV
BSDV
TDOI
The Nexus/JTAG Read/Write Access Control/Status Register (RWCS) write (to begin a
read access) or the write to the Read/Write Access Data Register (RWD) (to begin a write
access) does not actually begin its action until 1 JTAG clock (TCK) after leaving the JTAG
Update-DR state. This prevents the access from being performed and therefore will not
signal its completion via the READY (RDY) output unless the JTAG controller receives an
additional TCK. In addition, EVTI is not latched into the device unless there are clock
transitions on TCK.
JDC
Symbol
t
t
TDIS
TDIH
A
= T
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
L
Table 36
to T
DD
Table 35. JTAG pin AC electrical characteristics
C
P
D
P
P
P
C
D
P
P
P
P
D
P
P
= 1.14 V to 1.32 V, V
H,
T
Preliminary—Subject to Change Without Notice
MPC5644A Microcontroller Data Sheet, Rev. 4
and C
TCK Cycle Time
TCK Clock Pulse Width
TCK Rise and Fall Times (40% - 70%)
TMS, TDI Data Setup Time
TMS, TDI Data Hold Time
TCK Low to TDO Data Valid
TCK Low to TDO Data Invalid
TCK Low to TDO High Impedance
JCOMP Assertion Time
JCOMP Setup Time to TCK Low
TCK Falling Edge to Output Valid
TCK Falling Edge to Output Valid out
of High Impedance
TCK Falling Edge to Output High
Impedance
Boundary Scan Input Valid to TCK
Rising Edge
TCK Rising Edge to Boundary Scan
Input Invalid
for functional specifications.
L
= 30 pF with DSC = 0b10, SRC = 0b11. These specifications apply to JTAG
Characteristic
DDEH
NOTE
= 4.5 V to 5.5 V with multi-voltage pads programmed to
Value
Min.
100
100
25
25
40
25
40
5
0
3
3
1
Freescale Semiconductor
Value
Max.
22
22
50
50
50
60
3
2
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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