xc3s1400an Xilinx Corp., xc3s1400an Datasheet - Page 68

• Manufacturer Part Number: xc3s1400an
• Description: Spartan-3an Fpga Family Data Sheet
• Manufacturer: Xilinx Corp.

Pinout Descriptions
Table 60: Types of Pins on Spartan-3AN FPGAs (Continued)
Package Pins by Type
Each package has three separate voltage supply
inputs—VCCINT, VCCAUX, and VCCO—and a common
ground return, GND. The numbers of pins dedicated to
these functions vary by package, as shown in
Table 61: Power and Ground Supply Pins by Package
A majority of package pins are user-defined I/O or input
pins. However, the numbers and characteristics of these
I/Os depend on the device type and the package in which it
Table 62: Maximum User I/O by Package
68
Notes:
1.
Notes:
1.
TQG144
FTG256
FGG400
FGG484
FGG676
XC3S50AN
XC3S200AN
XC3S400AN
XC3S700AN
XC3S1400AN
Color Code
Package
VCCAUX
VCCINT
MGMT
Type /
VCCO
JTAG
PWR
GND
Device
# = I/O bank number, an integer between 0 and 3.
Some VREFs are on INPUT pins. See pinout tables for details.
N.C.
Control and status pins for the power-saving Suspend mode. SUSPEND is a dedicated pin.
AWAKE is a Dual-Purpose pin. Unless Suspend mode is enabled in the application, AWAKE is
available as a user-I/O pin.
Dedicated JTAG pin - 4 per device. Not available as a user-I/O pin. Every package has four
dedicated JTAG pins. These pins are powered by VCCAUX.
Dedicated ground pin. The number of GND pins depends on the package used. All must be
connected.
Dedicated auxiliary power supply pin. The number of VCCAUX pins depends on the package
used. The In-System Flash memory is powered by VCCAUX. All must be connected to +3.3V.
Dedicated internal core logic power supply pin. The number of VCCINT pins depends on the
package used. All must be connected to +1.2V.
Along with all the other VCCO pins in the same bank, this pin supplies power to the output buffers
within the I/O bank and sets the input threshold voltage for some I/O standards. All must be
connected.
This package pin is not connected in this specific device/package combination.
VCCINT
Package
TQG144
FGG400
FGG484
FGG676
FTG256
15
23
4
6
9
VCCAUX
Input-Only
Maximum
User I/Os
10
14
4
4
8
and
108
195
311
372
502
VCCO
Maximum
16
22
24
36
8
Input-
Only
Table
35
63
84
94
7
Description
61.
GND
13
28
43
53
77
www.xilinx.com
Differential
Maximum
Pairs
142
165
227
50
90
is available, as shown in
maximum number of single-ended I/O pins available,
assuming that all I/O-, INPUT-, DUAL-, VREF-, and
CLK-type pins are used as general-purpose I/O. AWAKE is
counted here as a Dual-Purpose I/O pin. Likewise, the table
shows the maximum number of differential pin-pairs
available on the package. Finally, the table shows how the
total maximum user-I/Os are distributed by pin type,
including the number of unconnected—N.C.—pins on the
device.
Not all I/O standards are supported on all I/O banks. The left
and right banks (I/O banks 1 and 3) support higher output
drive current than the top and bottom banks (I/O banks 0
and 2). Similarly, true differential output standards, such as
LVDS, RSDS, PPDS, miniLVDS, and TMDS, are only
supported in the top or bottom banks (I/O banks 0 and 2).
Inputs are unrestricted. For more details, see the “Using I/O
Resources” chapter in UG331.
155
194
313
I/O
42
69
INPUT
21
46
61
67
2
All Possible I/Os by Type
DUAL
Table
26
52
52
52
52
62. The table shows the
DS557-4 (v3.1) June 2, 2008
VREF
21
26
33
38
8
SUSPEND, AWAKE
TDI, TMS, TCK, TDO
GND
VCCAUX
VCCINT
VCCO_#
N.C.
Pin Name(s) in Type
Product Specification
CLK
30
32
32
32
32
N.C.
17
0
0
0
3
R