xc3s1400an Xilinx Corp., xc3s1400an Datasheet - Page 52

• Manufacturer Part Number: xc3s1400an
• Description: Spartan-3an Fpga Family Data Sheet
• Manufacturer: Xilinx Corp.

DC and Switching Characteristics
Miscellaneous DCM Timing
Table 43: Miscellaneous DCM Timing
DNA Port Timing
Table 44: DNA_PORT Interface Timing
Internal SPI Access Port Timing
Table 45: SPI_ACCESS Interface Timing
52
Notes:
1.
Notes:
1.
2.
3.
DCM_RST_PW_MIN
DCM_RST_PW_MAX
DCM_CONFIG_LAG_TIME
T
T
T
T
SPICCK_MOSI
SPICKC_MOSI
T
T
(T
SPICCK_CSB
SPICCK_CSB
T
T
The minimum READ pulse width is 5 ns, the maximum READ pulse width is 10
This limit only applies to applications that use the DCM DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV).
The DCM DFS outputs (CLKFX, CLKFX180) are unaffected.
This specification is equivalent to the Virtex
This specification is equivalent to the Virtex-4 TCONFIG specification. This specification does not apply for Spartan-3AN FPGAs.
T
T
(T
T
(T
Symbol
Symbol
T
T
(T
T
DNADCKO
DNACLKH
DNACLKF
DNACLKL
DNADSU
DNARSU
DNASSU
MOSISU
DNADH
DNARH
T
DNASH
CSBSU
MOSIH
CSBH
CSB
)
)
)
)
Symbol
Setup time on SHIFT before the rising edge of CLK
Hold time on SHIFT after the rising edge of CLK
Setup time on DIN before the rising edge of CLK
Hold time on DIN after the rising edge of CLK
Setup time on READ before the rising edge of CLK
Hold time on READ after the rising edge of CLK
Clock-to-output delay on DOUT after rising edge of CLK
CLK frequency
CLK High time
CLK Low time
Setup time on MOSI before the active edge of CLK
Hold time on MOSI after the active edge of CLK
CSB High time
Setup time on CSB before the active edge of CLK
Hold time on CSB after the active edge of CLK
(2)
(3)
Minimum duration of a RST pulse width
Maximum duration of a RST pulse width
Maximum duration from V
configuration successfully completed (DONE pin goes High)
and clocks applied to DCM DLL
Description
™
-4 DCM_RESET specification. This specification does not apply for Spartan-3AN FPGAs.
Description
www.xilinx.com
Description
CCINT
applied to FPGA
μs
.
4.47
4.03
7.15
7.15
Min
50
-5
Max
Speed Grade
–
–
–
–
–
Min
1.0
0.5
1.0
0.5
5.0
0.5
1.0
1.0
0
0
Min
N/A
N/A
N/A
N/A
3
DS557-3 (v3.1) June 2, 2008
Min
5.0
4.5
8.0
8.0
50
10,000
Product Specification
Max
100
1.5
-4
∞
∞
–
–
–
–
–
Max
N/A
N/A
N/A
N/A
–
Max
–
–
–
–
–
seconds
seconds
minutes
minutes
Units
CLKIN
MHz
cycles
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
ns
ns
ns
ns
ns
R