xc3s1400an Xilinx Corp., xc3s1400an Datasheet - Page 67

• Manufacturer Part Number: xc3s1400an
• Description: Spartan-3an Fpga Family Data Sheet
• Manufacturer: Xilinx Corp.

DS557-4 (v3.1) June 2, 2008
Introduction
This section describes how the various pins on a
Spartan
component packages, and provides device-specific thermal
characteristics. For general information on the pin functions
and the package characteristics, see the Packaging section
of UG331:
•
Spartan-3AN FPGAs are available in Pb-free, RoHS
packages, indicated by a “G” in the middle of the package
code. Leaded (non-Pb-free) packages may be available for
selected devices, with the same pin-out and without the "G"
Table 60: Types of Pins on Spartan-3AN FPGAs
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property of their respective owners.
DS557-4 (v3.1) June 2, 2008
Product Specification
Color Code
CONFIG
INPUT
Type /
DUAL
VREF
UG331: Spartan-3 Generation FPGA User Guide
http://www.xilinx.com/support/documentation/
user_guides/ug331.pdf
CLK
I/O
®
-3AN FPGA connect within the supported
Unrestricted, general-purpose user-I/O pin. Most pins can be paired together to form differential
I/Os.
Unrestricted, general-purpose input-only pin. This pin does not have an output structure.
Dual-purpose pin used in some configuration modes during the configuration process and then
usually available as a user I/O after configuration. If the pin is not used during configuration, this
pin behaves as an I/O-type pin. See UG332: Spartan-3 Generation Configuration User Guide for
additional information on these signals.
Dual-purpose pin that is either a user-I/O pin or Input-only pin, or, along with all other VREF pins
in the same bank, provides a reference voltage input for certain I/O standards. If used for a
reference voltage within a bank, all VREF pins within the bank must be connected.
Either a user-I/O pin or an input to a specific clock buffer driver. Most packages have 16 global
clock inputs that optionally clock the entire device. The exception is the TQ144 package). The
RHCLK inputs optionally clock the right half of the device. The LHCLK inputs optionally clock the
left half of the device. See the Using Global Clock Resources chapter in UG331: Spartan-3
Generation FPGA User Guide for additional information on these signals.
Dedicated configuration pin, two per device. Not available as a user-I/O pin. Every package has
two dedicated configuration pins. These pins are powered by VCCAUX. See the UG332:
Spartan-3 Generation Configuration User Guide for additional information on the DONE and
PROG_B signals.
R
Description
<BL
Blue
>
www.xilinx.com
0
in the ordering code; contact Xilinx sales for more
information. The Pb-free package code may be selected in
the software for the non-Pb-free packages since the pinouts
are identical.
Pin Types
Most pins on a Spartan-3AN FPGA are general-purpose,
user-defined I/O pins. There are, however, up to 12 different
functional types of pins on Spartan-3AN FPGA packages,
as outlined in
that follow, the individual pins are color-coded according to
pin type as in the table.
Spartan-3AN FPGA Family:
Table
60. In the package footprint drawings
Pinout Descriptions
Product Specification
IO_#
IO_Lxxy_#
IP_#
IP_Lxxy_#
M[2:0]
PUDC_B
CCLK
MOSI/CSI_B
D[7:1]
D0/DIN
DOUT
CSO_B
RDWR_B
INIT_B
A[25:0]
VS[2:0]
LDC[2:0]
HDC
IP/VREF_#
IP_Lxx_#/VREF_#
IO/VREF_#
IO_Lxx_#/VREF_#
IO_Lxx_#/GCLK[15:0],
IO_Lxx_#/LHCLK[7:0],
IO_Lxx_#/RHCLK[7:0]
DONE, PROG_B
Pin Name(s) in Type
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