xc3s1400an Xilinx Corp., xc3s1400an Datasheet - Page 3

• Manufacturer Part Number: xc3s1400an
• Description: Spartan-3an Fpga Family Data Sheet
• Manufacturer: Xilinx Corp.

DS557-1 (v3.1) June 2, 2008
Introduction
The Spartan-3AN FPGA family combines the best attributes
of a leading edge, low cost FPGA with nonvolatile
technology across a broad range of densities. The family
combines all the features of the Spartan-3A FPGA family
plus leading technology in-system Flash memory for
configuration and nonvolatile data storage.
The
space-constrained applications such as blade servers,
medical devices, automotive infotainment, telematics, GPS,
and other small consumer products. Combining FPGA and
Flash technology minimizes chip count, PCB traces and
overall size while increasing system reliability.
The Spartan-3AN FPGA internal configuration interface is
completely self-contained, increasing design security. The
family maintains full support for external configuration. The
Spartan-3AN FPGA is the world’s first nonvolatile FPGA
with MultiBoot, supporting two or more configuration files in
one device, allowing alternative configurations for field
upgrades, test modes, or multiple system configurations.
Features
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Table 1: Summary of Spartan-3AN FPGA Attributes
Notes:
1.
2.
© 2007-2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. PCI is a trademark of PCI-SIG.
All other trademarks are the property of their respective owners.
DS557-1 (v3.1) June 2, 2008
Product Specification
XC3S50AN
XC3S200AN
XC3S400AN
XC3S700AN
XC3S1400AN 1400K
Device
The new standard for low cost nonvolatile FPGA solutions
Eliminates traditional nonvolatile FPGA limitations with the
advanced 90 nm Spartan-3A device feature set
♦
Integrated robust configuration memory
♦
♦
♦
♦
Plentiful amounts of nonvolatile memory available to the user
♦
♦
♦
♦
Robust 100K Flash memory program/erase cycles
By convention, one Kb is equivalent to 1,024 bits and one Mb is equivalent to 1,024 Kb.
The XC3S400AN and the XC3S700AN have the same number of block RAMs and multipliers because the XC3S700AN adds DCMs as shown in
Figure
Spartan-3AN
Memory, multipliers, DCMs, SelectIO, hot swap, power
management, etc.
Saves board space
Improves ease-of-use
Simplifies design
Reduces support issues
Up to 11+ Mb available
MultiBoot support
Embedded processing and code shadowing
Scratchpad memory
1.
System
Gates
200K
400K
700K
50K
Equivalent
FPGA
13,248
25,344
Logic
1,584
4,032
8,064
Cells
R
family
CLBs
1472
2816
176
448
896
<
B
L
11,264
Slices
3,584
5,888
1792
is
704
excellent
RAM bits
Distributed
176K
11K
28K
56K
92K
(1)
www.xilinx.com
Introduction and Ordering Information
for
bits
Block
288K
360K
360K
576K
RAM
54K
(1)
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•
•
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Multipliers DCMs
Dedicated
20 years Flash memory data retention
Security features provide bitstream anti-cloning protection
♦
♦
♦
Configuration watchdog timer automatically recovers from
configuration errors
Suspend mode reduces system power consumption
♦
♦
Full hot-swap compliance
Multi-voltage, multi-standard SelectIO™ interface pins
♦
♦
♦
♦
♦
♦
♦
♦
Abundant, flexible logic resources
♦
♦
♦
Hierarchical SelectRAM™ memory architecture
♦
♦
Up to eight Digital Clock Managers (DCMs)
Eight global clocks and eight additional clocks per each half
of device, plus abundant low-skew routing
Complete Xilinx
development system support
MicroBlaze™ and PicoBlaze™ embedded processor cores
Fully compliant 32-/64-bit 33 MHz PCI™ technology support
Low-cost QFP and BGA Pb-free (RoHS) packaging options
♦
16
20
20
32
3
Buried configuration interface
Unique Device DNA serial number in each device for
design Authentication to prevent unauthorized copying
Flash memory sector protection and lockdown
Retains all design state and FPGA configuration data
Fast response time, typically less than 100 μs
Up to 502 I/O pins or 227 differential signal pairs
LVCMOS, LVTTL, HSTL, and SSTL single-ended signal
standards
3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling
Up to 24 mA output drive
3.3V±10% compatibility and hot swap compliance
622+ Mb/s data transfer rate per I/O
DDR/DDR2 SDRAM support up to 400 Mb/s
LVDS, RSDS, mini-LVDS, PPDS, HSTL/SSTL differential
I/O
Densities up to 25,344 logic cells
Optional shift register or distributed RAM support
Enhanced 18 x 18 multipliers with optional pipeline
Up to 576 Kbits of dedicated block RAM
Up to 176 Kbits of efficient distributed RAM
Pin-compatible with Spartan-3A FPGA family
Spartan-3AN FPGA Family:
2
4
4
8
8
ISE
Maximum
User I/O
®
108
195
311
372
502
and WebPACK™ software
Differential
Maximum
I/O Pairs
142
165
227
50
90
Product Specification
Bitstream
1,168K
1,842K
2,669K
4,644K
Size
427K
(1)
In-System
Flash bits
16M
1M
4M
4M
8M
3