dsp56167 Freescale Semiconductor, Inc, dsp56167 Datasheet - Page 93

• Manufacturer Part Number: dsp56167
• Description: Advance Information 16-bit Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
PERIPHERAL ADDRESS GENERATION UNIT (PAGU)
A Peripheral Address Generation Unit (PAGU) has been added to the DSP56167. The
PAGU allows the DSP to generate external peripheral addresses. To support this
function, some control bits have been added to DSP56100 core registers and a number
of new core registers and functional units have been added.
Core changes to support the PAGU include:
The interrupt feature of the PAGU can be enabled by programming the two interrupt
enable/priority encoding bits in the IPR2 register. The PAGU interrupt can also be
de-asserted if the Peripheral Enable (PE) bit 9 of the Operating Mode Register (OMR),
(i.e., the PAGU is disabled). Since the hardware reset clears PE, it also deasserts the
PAGU interrupt request.
Once the PAGU is enabled, every time a post update operation occurs, the post
updated address will be compared against the value in the corresponding PAC
register. When the two values matched, an interrupt request signal will be asserted.
When the DSP core recognizes the PAGU interrupt, the interrupt vector
corresponding to the updated Peripheral Address Pointer is taken. Its corresponding
interrupt request signal is cleared as the interrupt is being serviced. If the Peripheral
Address Pointer and/or the PAC register pair values are changed before the
corresponding interrupt is serviced, the interrupt will remain pending.
• Defined Interrupt Priority Register (IPR2) bits 1 and 0—this is the DSP
• New Registers—These registers and pointers are used as matched pairs (i.e.,
• New Units—There are two new processing units:
• New Interrupt Vectors—There are 3 separate interrupt vectors, one for each
second X memory mapped interrupt priority register at address X:$FFDD.
PAGUR0 is used with PAGUC0):
–
–
–
–
Peripheral Address Compare Register, located at addresses P:$0030, P:$0032
and P:$0034, respectively.
Special Design Considerations for Conversions from DSP56166 to DSP56167
Peripheral Address Generation Unit Registers (pointers) 0–2 (PAGUR0–
PAGUR2]
Peripheral Address Generation Unit Compare registers 0–2 (PAGUC0–
PAGUC2]
Post Update Address Generation Unit (PUAGU) supports three post-
update modes:
• No Update [(Rn)],
• Post-increment [(Rn)+], and
• Post-decrement [(Rn)–]
Comparator—Address Comparator and Interrupt Control Unit.
DSP56167/D, Rev. 1
Design Considerations
4-17