dsp56167 Freescale Semiconductor, Inc, dsp56167 Datasheet - Page 35

• Manufacturer Part Number: dsp56167
• Description: Advance Information 16-bit Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
Note:
Num
R/W, BS
D0–D15
A0–A15,
BS, R/W
A0–A15
PEREN
RESET
PEREN
RESET
PS/DS
PS/DS
CLKO
Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing (60 MHz) (Continued)
3.
4.
1.
2.
5.
6.
7.
Circuit stabilization delay is required during reset when using an external clock in two cases:
• after power-on reset, and
• when recovering from Stop mode.
When using fast interrupts and IRQA and IRQB are defined as level-sensitive, then timings 20 and
21 apply to prevent multiple interrupt service. To avoid these timing restrictions, the Deasserted
Edge-Triggered mode is recommended when using fast interrupt. Long interrupts are
recommended when using Level-Sensitive mode.
The interrupt instruction fetch is visible on the pins only in Mode 3.
The minimum is specified for the duration of an edge triggered IRQA interrupt required to
recover from the Stop state. This is not the minimum required so that the IRQA interrupt is
accepted.
Timing 22 is for all IRQx interrupts while timing #23 is only when exiting the Wait state
Timing 22 triggers off T1 in the normal state and off phi1 when exiting the Wait state.
The instruction fetch is visible on the pins only in Mode 2 and Mode 3.
10
13
Characteristics
Figure 2-4 Asynchronous Reset Timing
Figure 2-5 Synchronous Reset Timing
DSP56167/D, Rev. 1
11
RESET, Stop, Mode Select, and Interrupt Timing
14
Min
12
First Fetch
Max
V
IHR
Specifications
AA0775
AA0776
Unit
2-9