dsp56167 Freescale Semiconductor, Inc, dsp56167 Datasheet - Page 44

• Manufacturer Part Number: dsp56167
• Description: Advance Information 16-bit Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

Specifications
Bus Arbitration Timing—Slave Mode
BUS ARBITRATION TIMING—SLAVE MODE
V
2-18
No.
DD
70 BR Input to CLKO low setup time
71 Delay from BR Input Assertion to BG Output Assertion
72 CLKO high to BG Output Assertion
73 BG Output Deassertion duration for two consecutive BR
74 CLKO High to Control Bus high impedance
75 CLKO High to BB Output Deassertion
76 CLKO High to BB Output (tri-stated)
77 BR Input Deassertion to BG Output Deassertion
78 CLKO High to BG Deassertion
79 CLKO High to BB Output Active
80 CLKO High to BB Output Assertion
81 CLKO High to Address and Control Bus Active
82 CLKO High to Address and Control Bus Valid
cyc = Clock cycle = 1/2 instruction cycle = 2 T cycles
WS = Number of Wait States for X or P external memory, determined by BCR or BCR2
WT = WS cyc = 2T WS
W
W
= 5.0 V 10%; TJ = –40 to +115˚C; CL = 50 pF + 1 TTL load
X
P
= Number of Wait States for P external memory, determined by BCR (WS = 0 to 31)
= Number of Wait States for X external memory, determined by BCR or BCR2
External read or write access
External read-modify-write access
Stop mode—external bus released and BG asserted
Wait mode
No external access by the DSP
External read or write access
External read-modify-write access
Stop mode—external bus released and BG asserted
Wait mode
External DSP accesses pending
(WS = 0 to 31)
(WS = 0 to 31)
No external access by the DSP
Table 2-10 Slave Mode Bus Arbitration Timing
Characteristics
DSP56167/D, Rev. 1
5T + 6.6
3T + 6.6
5T + 6.6
5T + 3.7
5T + 3.7
5T + 3.4
2T + 3.3
3T + 3.4
T+6.6
Min
2.8
7.0
1.0
1.0
25
—
—
—
—
—
—
—
—
—
60 MHz
26T+ 4T x W
2T x W
9T+WT+3.1
3T + 2.7
9T +3.1
Max
10.2
18.0
15.0
8.0
8.5
9.4
9.7
—
—
—
—
—
—
—
—
—
—
—
—
P
+ 2.7
MOTOROLA
X
+
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns