dsp56167 Freescale Semiconductor, Inc, dsp56167 Datasheet - Page 12

• Manufacturer Part Number: dsp56167
• Description: Advance Information 16-bit Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

Signal/Pin Descriptions
Data Bus
DATA BUS
BUS CONTROL
1-6
D0–D15
BS
PS/DS
PEREN
WR
Signal
Name
Names
Signal
Output Pulled
Output Tri-stated Program/Data Memory Select—This signal is asserted high for
Output Tri-stated Peripheral Enable—This output is asserted only when the external
Output Tri-stated Write Enable—WR is asserted low during external memory write
Signal
Type
Output
Signal
Input/
Type
high
during
Reset
State
Tri-stated Data Bus—These signals provide the bidirectional data bus for
during
Reset
State
Bus Select—BS is asserted when the DSP accesses the external bus,
and it acts as an early indication of imminent external bus access by
the DSP56167. It may also be used with the bus wait input WT to
generate wait states. BS is pulled high when the BG or RESET signal
is asserted.
external program memory access and low for external data memory
access. The timing is the same as for the Address Bus signals A0–
A15. If the external bus is not used during an instruction cycle, PS/
DS goes high at the next T0.
peripheral data memory space (X:$FF00–X:$FF7F) is referenced. The
timing is the same as for the Address Bus signals A0–A15. The
signal is asserted and deasserted in T0. PEREN is driven high for
any program space access and for any data memory access outside
of the peripheral data memory address range.
cycles. When WR is asserted in T1, the data bus signals (D0–D15)
become outputs. The DSP puts data on the bus on the leading edge
of T2. When WR is deasserted in T3, the data should be latched in
the external device. The signal qualifies A0–A15 and PS/DS. WR is
tri-stated when the DSP is not the bus master. WR can be connected
directly to the WE pin of a Static RAM chip.
Table 1-7 Bus Control Signals
external program and data memory accesses. Read data is
sampled in by the trailing edge of T2, while write data output is
enabled by the leading edge of T2 and tri-stated at the leading
edge of T0. D0–D15 are tri-stated when there is no bus activity.
Table 1-6 Data Bus Signals
DSP56167/D, Rev. 1
Signal Description
Signal Description
MOTOROLA