dsp56167 Freescale Semiconductor, Inc, dsp56167 Datasheet - Page 102

• Manufacturer Part Number: dsp56167
• Description: Advance Information 16-bit Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

Design Considerations
Special Design Considerations for Conversions from DSP56166 to DSP56167
4-26
Restrictions
INDEPENDENT EXTERNAL CHIP ENABLE SIGNALS BR AND PEREN
The following restrictions apply when using this feature:
On the DSP56166, while the DSP is in the Master Mode of bus operation, BR is
asserted for each external memory and external peripheral accesses. When the
external peripheral space is accessed, PEREN is also asserted. As a result, it is
possible to use BR as an external chip enable. However, since both BR and PEREN are
asserted for external peripheral space accesses, it is not possible to disable or power-
down an external memory versus an external peripheral separately.
The DSP56167 independent chip enable feature allows the DSP to disable or power
down the external memory when it is not being accessed even when the external
peripheral device is being accessed. As before, the external peripheral device can be
disabled using the PEREN pin since this signal is deasserted high whenever the
external peripheral space is not being accessed.
This feature is enabled when the CHIPEN bit 15 of the Bus Control Register2,
(BCR2[15]) is set to 1. It is disabled when CHIPEN is cleared. While in the Bus Master
mode of operation (i.e., bit 2 of the OMR is set), the user has the option of enabling BR
and PEREN to act as two independent external chip enable signals.
Note: This feature is not available while the chip is in the Bus Slave Mode of
• During move from peripheral to X memory instruction, the X memory
• During moves to and from program memory, the program memory address is
• It is illegal to use (r3), (r3)+, (r3)-, and (Rn)+Nn addressing modes when the
• Modulo or reverse carry addressing modes is not allowed.
• Must wait one instruction cycle before using the values written to the
• Must wait one instruction cycle before using the PAGU/Core addressing
address comes from the PAGU and the peripheral address comes from the
Core AALU.
output from the Core AALU and the X memory source or destination address,
if needed, is output from the PAGU.
PAGU is active and the R3 part of the move is not associated with a parallel
move.
PAGURn & PAGUCn registers.
modes after the OMR[PE] and/or SR[AD} bits are changed.
operation, (i.e., OMR[2] is cleared).
DSP56167/D, Rev. 1
MOTOROLA