dsp56167 Freescale Semiconductor, Inc, dsp56167 Datasheet - Page 89

• Manufacturer Part Number: dsp56167
• Description: Advance Information 16-bit Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

HOST PORT USAGE CONSIDERATIONS
Host Programmer Considerations
MOTOROLA
Careful synchronization is required when reading multibit registers that are written
by another asynchronous system. This is a common problem when two
asynchronous systems are connected. The situation exists in the Host port. The
considerations for proper operation are discussed below.
Note: A potential problem exists when reading status bits HF3 and HF2 as an
• Unsynchronized Reading of Receive Byte Registers—When reading receive
• Overwriting Transmit Byte Registers—The host programmer should not
• Synchronization of Status Bits from DSP to Host—HC, HREQ, DMA, HF3,
byte registers, RXH or RXL, the host programmer should use interrupts or
poll the RXDF flag which indicates that data is available. This assures that the
data in the receive byte registers will be stable.
write to the transmit byte registers, TXH or TXL, unless the TXDE bit is set
indicating that the transmit byte registers are empty. This guarantees that the
transmit byte registers will transfer valid data to the HRX register.
HF2, TRDY, TXDE, and RXDF (refer to DSP56167 User’s Manual ,
I/O Interface section, Host/DMA Interface Programming Model for
descriptions) status bits are set or cleared from inside the DSP and read by the
host processor. The Host can read these status bits very quickly without
regard to the clock rate used by the DSP, but the possibility exists that the
state of the bit could be changing during the read operation. This is generally
not a system problem, since the bit will be read correctly in the next pass of
any Host polling routine.
However, if the Host asserts the HEN for more than timing number 101
(T101), with a minimum cycle time of timing number 103 (T103), then the
status is guaranteed to be stable.
encoded pair. If the DSP changes HF3 and HF2 from 00 to 11, there is a small
probability that the Host could read the bits during the transition and receive
01 or 10 instead of 11. If the combination of HF3 and HF2 has significance, the
Host could read the wrong combination.
Solution:
a. Read the bits twice and check for consensus.
b. Assert HEN access for T101a so that status bit transitions are stabilized.
DSP56167/D, Rev. 1
Host Port Usage Considerations
Design Considerations
4-13