adsp-21535 STMicroelectronics, adsp-21535 Datasheet - Page 48

• Manufacturer Part Number: adsp-21535
• Description: Dsm Digital Signal Processor System Memory For Analog Devices Dsps 3.3v Supply
• Manufacturer: STMicroelectronics

DSM2150F5V
RESET TIMING AND DEVICE STATUS AT RESET
Power On Reset
Upon Power-up, the device requires a Reset (
SET
steady. During this time period, the device loads
internal configurations, clears some of the regis-
ters and sets the Flash memory into Read Array
Mode. After the rising edge of Reset (
device remains in the Reset Mode for an additional
period, t
lowed.
Upon Power On reset, internal sector selects FS0-
7 and CSBOOT0-7 must all be inactive and Write
Strobe (
mum security of the data contents and to remove
the possibility of a byte/word being written on the
first edge of Write Strobe (
memory WRITE cycle initiation is prevented auto-
matically when V
Figure 22. Reset (RESET) Timing
Table 14. Status During Power-on Reset, Warm Reset and Power-down Mode
48/73
MCU I/O
PLD Output
PMMR0 and PMMR2
OMC Flip-flop status
All other registers
) pulse of duration t
V
RESET
CC
OPR
WR
Port Configuration
, CNTL0) inactive (logic ’1’) for maxi-
, before the first memory access is al-
Register
CC
is below V
Power-On Reset
V
t NLNH-PO
CC
WR
(min)
NLNH-PO
, CNTL0). Any Flash
LKO
.
Input Mode
Valid after internal PSD configuration
bits are loaded (almost immediately)
Cleared to ’0’
Cleared to ’0’ by internal Power-on
Reset
Cleared to ’0’
after V
RESET
t OPR
CC
), the
Power-on Reset
Power-on Reset
RE-
is
Warm Reset
Once the device is up and running, the device can
be reset with a pulse of a much shorter duration,
t
device is operational after warm reset. Figure
shows the timing of the Power-up and warm reset.
I/O Pin, Register, and PLD Status at Reset
Table
tus during Power-on Reset, warm reset and Pow-
er-down Mode. PLD outputs are always valid
during warm reset, and they are valid in Power On
Reset once the internal device Configuration bits
are loaded. This loading of the device is completed
typically long before the V
ing level. Once the PLD is active, the state of the
outputs are determined by the PSDsoft Express
equations.
NLNH
. The same t
14
shows the I/O pin, register and PLD sta-
Input Mode
Valid
Unchanged
Depends on .re and .pr equations
Cleared to ’0’
OPR
Warm Reset
t NLNH-A
t NLNH
period is needed before the
CC
Warm Reset
Warm Reset
ramps up to operat-
t OPR
AI02866b
22