adsp-21535 STMicroelectronics, adsp-21535 Datasheet - Page 24

• Manufacturer Part Number: adsp-21535
• Description: Dsm Digital Signal Processor System Memory For Analog Devices Dsps 3.3v Supply
• Manufacturer: STMicroelectronics

DSM2150F5V
PLDs
The PLDs bring programmable logic to the device.
After specifying the logic for the PLDs using PSD-
soft Express, the logic is programmed into the de-
vice and available upon Power-up.
The PLDs have selectable levels of performance
and power consumption.
The device contains two PLDs: the Decode PLD
(DPLD), and the Complex PLD (CPLD), as shown
in
The DPLD performs address decoding, and gen-
erates select signals for internal and external com-
ponents, such as memory, registers, and I/O ports.
The DPLD can generate eight External Chip Se-
lect (ECS0-ECS7) signals on Port C.
The CPLD can be used for logic functions, such as
loadable counters and shift registers, state ma-
chines, and encoding and decoding logic. These
logic functions can be constructed using the 16
Output Macrocells (OMC), 24 Input Macrocells
(IMC), and the AND Array.
The AND Array is used to form product terms.
These product terms are configured from the logic
definition entered in PSDsoft Express. A PLD In-
put Bus consisting of 73 signals is connected to
the PLDs. Input signals are shown in Table 10.
Turbo Bit
The PLDs in the device can minimize power con-
sumption by switching to standby when inputs re-
main unchanged for an extended time t
Resetting the Turbo Bit to ’0’ (Bit 3 of the PMMR0
register) automatically places the PLDs into stand-
by if no inputs are changing. Turning the Turbo
Mode off increases propagation delays while re-
ducing power consumption. Additionally, seven
bits are available in the PMMR registers in csiop to
24/73
Figure 6., page
25.
TURBO
.
block DSP control signals from entering the PLDs.
This reduces power consumption and can be used
only when these DSP control signals are not used
in PLD logic equations. Each of the two PLDs has
unique characteristics suited for its applications.
They are described in the following sections.
Table 10. DPLD and CPLD Inputs
Note: 1. DSP address lines above A15 may enter the DSM device
DSP Address Bus
DSP Control Signals
Reset
PortA Input Macrocells PA7-PA0
PortB Input Macrocells
PortC Input Macrocells
Port D Inputs
Page Register
Macrocell A Feedback
Macrocell B Feedback
Flash memory
Program Status Bit
Input Source
2. Additional DSP control signals may enter the DMS device
on any pin on ports A, B, C or D. See Appendices for rec-
ommended connections.
on any pin on Ports A, B, C, or D. See Appendices for rec-
ommended connections.
1
2
A15-A0
CNTL2-CNTL0
RST
PB7-PB0
PC7-PC0
PD3-PD0
PG7-PG0
MCELLA FB7-0
MCELLB FB7-0
Ready/Busy
Input Name
Number
Signals
16
of
3
1
8
8
8
4
8
8
8
1