adsp-21535 STMicroelectronics, adsp-21535 Datasheet
adsp-21535
Related parts for adsp-21535
adsp-21535 Summary of contents
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... DSM (Digital Signal Processor System Memory) FEATURES SUMMARY Glueless Connection to DSP – Easily add memory, logic, and I/O to the External Port of ADSP-218x, 219x, 2106x, 2116x, 2153x, and TS101 families of DSPs from Analog Devices, Inc. Dual Flash Memories – Two independent Flash memory arrays for storing DSP code and data – ...
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DSM2150F5V TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... The Output Enable of the OMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Input Macrocells (IMC DSP BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Typical Memory Map, DSM2150F5V and ADSP21535 BLACKFIN DSP Specifying the Memory Map with PSDsoft Express™ ADSP-21535 Blackfin DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 ADSP-21062 SHARC DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 ADSP-TS101S TigerSHARC DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 ADSP-2191 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 ADSP-2188M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 General Port Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Port Operating Modes ...
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DSM2150F5V PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... ADSP-2116x SDRAM ADSP-TS101S HOST MCU JTAG DEBUG (All But ADSP-218x Family) DSM devices add programmable logic (PLD) and configurable I/O pins to the DSP system. The state of I/O pins can be driven by DSP soft- ware or PLD logic. PLD and I/O configuration are programmable by JTAG ISP. The PLD consists of more than 3000 gates and has 16 macro cell reg- isters ...
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... Table 2. Compatible Analog Devices DSPs DSP Part Number ADSP-2183, 2184L, 2185L, 2186L, 2187L ADSP-2185M, 2186M, 2188M, 2189M ADSP-2184N, 2185N, 2186N, 2187N, 2188N, 2189N ADSP-2191M, 2195M, 2196M Blackfin ADSP-21532S Blackfin ADSP-21535P Sharc ADSP-21060L, 21061L, 21062L, 21065L Sharc ADSP-21160M Sharc ADSP-21160N, 21161N Tiger Sharc ADSP-TS101S 6/73 Secondary ...
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Figure 3. TQFP Connections PD2 1 PD3 2 AD0 3 AD1 4 AD2 5 AD3 6 AD4 7 GND AD5 10 AD6 11 AD7 12 AD8 13 AD9 14 AD10 15 AD11 16 AD12 17 AD13 ...
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DSM2150F5V PIN DESCRIPTION Table 3. Pin Description (Pin Assignments in Appendix A) Pin Name Type AD0-15 In Sixteen address inputs from the DSP. Active low WRITE strobe input from the DSP, typically connected to DSP WR signal. CNTL0 In Also ...
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Pin Name Type Eight configurable Port E signals with the following functions: – MCU I/O – DSP may write or read pins directly at runtime with csiop registers. – PE0, PE1, PE2, and PE3 can form the JTAG IEEE-1149.1 ISP ...
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DSM2150F5V ARCHITECTURAL OVERVIEW Major functional blocks are shown in Figure 4. DSP Address/Data/Control Interface These DSP signals attach directly to the DSM for a glueless connection. An 8-bit or 16-bit data con- nection is formed and 16 or more DSP ...
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Main Flash Memory The 4M bit (512 KByte) Main Flash memory is di- vided into eight equally-sized 64 KByte sectors that are individually selectable through the De- code PLD. Each Flash memory sector can be lo- cated at any address ...
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... TERR in addition to TMS, TCK, TDI and TDO. ™ The FlashLINK JTAG programming cable is available from STMicroelectronics for $USD59 and PSDsoft Express software is available at no charge from www.st.com/psm. That is all that is needed to program a DSM device using the paral- lel port on any PC or notebook. See ...
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RUNTIME CONTROL REGISTER DEFINITION A block of 256 addresses are decoded inside the DSM2150F5V for control and status. 50 locations contain registers that the DSP accesses at runt- ime. The base address of the registers is called csiop (Chip Select ...
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DSM2150F5V DETAILED OPERATION Figure 4., page 10 shows major functional areas of the device: Flash Memories PLDs (DPLD, CPLD, Page Register) DSP Bus Interface (Address, Data, Control) I/O Ports Runtime Control Registers JTAG ISP Interface The following describes these functions ...
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Table 5. Instruction Sequences for 8-bit Operation (Notes 1,2,3,4) Instruction Cycle 1 Sequence Read byte Read Memory from any 5 valid Flash Contents memory addr Read Flash Write AAh to Identifier (Main XX555h 6,7 Flash only) Read Memory Write AAh ...
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DSM2150F5V 6. The Reset Flash instruction is required to return to the normal Read Array Mode if the Error Flag Bit (DQ5) goes High, or after read- ing the Flash Identifier or after reading the Sector Protection Status. 7. The ...
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Table 6. Instruction Sequences for 16-bit Operation (Notes 1,2,3,4,15) Instruction Cycle 1 Sequence Read word Read Memory from even 5 Contents addr Read Flash Write XXAAh Identifier (Main to XXAAAh 6,7 Flash only) Read Sector Write XXAAh 6,7,8 to XXAAAh ...
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DSM2150F5V 7. The DSP cannot invoke this instruction sequence while executing code from the same Flash memory as that for which the instruc- tion sequence is intended. The DSP must fetch, for example, the code from the DSP SRAM when ...
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INSTRUCTIONS An instruction sequence consists of a sequence of specific WRITE or READ operations. IMPORTANT: When the DSM2150F5V is configured for 8-bit op- erations, all instruction sequences consist of byte WRITE and READ operations on an even or odd address ...
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DSM2150F5V Reading Flash Memory Under typical conditions, the DSP may read the Flash memory using READ operations just as it would a ROM or RAM device. Alternately, the DSP may use READ operations to obtain status infor- mation about a ...
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Toggle Flag (DQ6) The device offers an alternative way for determin- ing when the Flash memory Program cycle is com- pleted. During the internal WRITE operation and when the Sector Select FS0-FS7 (or CSBOOT0- CSBOOT3) is true, the Toggle Flag ...
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DSM2150F5V PROGRAMMING FLASH MEMORY When the DSM2150F5V is configured for 8-bit op- eration, Flash memory locations are programmed in 8-bit bytes to even or odd addresses. When the DSM2150F5V is configured for 16-bit operation, Flash memory locations are pro- grammed ...
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Data Polling. Polling on the Data Polling Flag Bit (DQ7 method of checking whether a Program or Erase cycle is in progress or has completed. Figure 5 shows the Data Polling algorithm. When the DSP issues a Program ...
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DSM2150F5V PLDs The PLDs bring programmable logic to the device. After specifying the logic for the PLDs using PSD- soft Express, the logic is programmed into the de- vice and available upon Power-up. The PLDs have selectable levels of performance ...
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Figure 6. PLD Diagram 8 PAGE REGISTER Data Bus DECODE PLD (DPLD) 73 Output Macrocell Feedback 16 CPLD 73 Direct Macrocell Input to MCU Data Bus Input Macrocell and Input Ports 24 4 PORT D Inputs 8 Main Flash Memory ...
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DSM2150F5V Decode PLD (DPLD) The DPLD, shown in Figure 7, is used for decod- ing the address for internal and external compo- nents. The DPLD can be used to generate the following decode signals: 8 Main Flash memory Sector Select ...
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Complex PLD (CPLD) The CPLD can be used to implement system logic functions, such as loadable counters and shift reg- isters, system mailboxes, handshaking protocols, state machines, and random logic. See Applica- tion Note AN1171 for details on how to ...
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DSM2150F5V Output Macrocell (OMC) Eight of the OMCs, McellA0-McellA7, are connect Port A pins. The other eight Macrocells, McellB0-McellB7, are connected to Ports B pins. OMCs may be used for internal feedback (buried registers), or their outputs may ...
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Product Term Allocator The CPLD has a Product Term Allocator. PSDsoft ™ Express uses the Product Term Allocator to bor- row and place product terms from one Macrocell to another. This happens automatically in PSDsoft ™ Express , but understanding ...
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DSM2150F5V Figure 9. CPLD Output Macrocell MASK REG. Output Macrocell Allocator POLARITY SELECT PT CLK CLKIN Feedback ( .FB ) Port Input 30/73 INTERNAL DATA BUS ENABLE ( .OE ) PRESET ( .PR ...
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The OMC Mask Register There is one Mask Register for each of the two groups of eight OMCs. The Mask Registers can be used to block the loading of data to individual OMCs. The default value for the Mask Registers ...
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DSM2150F5V Figure 10. Input Macrocell ENABLE ( . Feedback 32/73 INTERNAL DATA BUS INPUT MACROCELL _ RD OUTPUT Macrocells BC AND Macrocells AB MUX LATCH DIRECTION REGISTER Port Driver PT ...
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... DSM2150F5V secondary Flash memory. While executing this code, the DSP will load the contents of the DSM2150F5V main Flash memory into the ADSP-21535 internal SRAM, then execute code from that high performance SRAM. The advantage of this is speed, flexibility, IAP, clean software partitioning, and parameter stor- age ...
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... DSM2150F5V Figure 11. Memory Map, ADSP-21535 34/73 9FFFF fs7 64K bytes Main Flash 90000 8FFFF fs6 64K bytes Main Flash 80000 7FFFF fs5 64K bytes Main Flash 70000 6FFFF fs4 64K bytes Main Flash 60000 5FFFF fs3 64K bytes Main Flash 50000 4FFFF ...
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Table 12. HDL Statements Generated from PSDsoft Express to Implement Memory Map csiop = ((address >= ^h10000) & (address <= ^h100FF) & (!_ams0)); fs0 = ((address >= ^h20000) & (address <= ^h2FFFF) & (!_ams0)); csiop = ((address >= ^h10000) & ...
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... DSM2150F5V ADSP-21535 Blackfin DSP Figure 13. Typical Connections, DSM2150F5V and ADSP-21535 Blackfin DSP 36/73 DSP JTAG DSM JTAG CONNECTOR CONNECTOR AI05777 ...
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... ADSP-21062 SHARC DSP Figure 14. Typical Connections, DSM2150F5V and ADSP-21062 SHARC DSP DSM2150F5V DSM JTAG DSP JTAG CONNECTOR CONNECTOR AI05780 37/73 ...
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... DSM2150F5V ADSP-TS101S TigerSHARC DSP Figure 15. Typical Connections, ADSP-TS101S TigerSHARC DSP 38/73 DSM JTAG DSP JTAG CONNECTOR CONNECTOR AI05779 ...
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... CNTL0 input to DSM2150F5V. This de- Figure 16. Typical Connections, DSM2150F5V and ADSP-2191M lays the falling edge HCLK is great- ever, the Write Hold Enable (E_WHE) memory space setting of the ADSP-2191 must be set to hold the DSP address after the delayed rising edge of DSM2150F5V to satisfy t WR ...
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... DSM2150F5V ADSP-2188M Figure 17. Typical Connections, DSM2150F5V and ADSP-2188M 40/73 DSM JTAG CONNECTOR AI05782 ...
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I/O PORTS There are seven programmable I/O ports: Ports and G. However, typically only four of these ports are available in 8-bit DSP data con- figuration, and 3 ports with 16-bit data. Each of ...
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DSM2150F5V Figure 18. General Port Architecture DATA OUT REG Macrocell Outputs EXT CS READ MUX DIR REG ENABLE PRODUCT TERM ( .OE ) CPLD-INPUT MCU I/O Mode In MCU I/O Mode, DSP I/O Ports are expanded. ...
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Drive Select Register The Drive Select Register configures the pin driver as Open Drain or CMOS (standard push/pull) for some port pins, and controls the slew rate for the other port pins. An external pull-up resistor should be used for ...
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DSM2150F5V Ports A, B, and C – Functionality and Structure Ports A and B have similar functionality and struc- ture, as shown in Figure19. The two ports can be configured to perform one or more of the following functions: MCU ...
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Port D – Functionality and Structure Port D has four I/O pins. See Figure 20. Port D can be configured to perform one or more of the follow- ing functions: MCU I/O Mode CPLD Input – direct input to the ...
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DSM2150F5V Port E – Functionality and Structure Port E can be configured to perform one or more of the following functions (see Figure 21): MCU I/O Mode In-System Programming (ISP) – JTAG port can be enabled for programming/erase of the ...
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POWER MANAGEMENT The device offers configurable power saving op- tions. These options may be used individually or in combinations, as follows: – All memory blocks in the device are built with zero-power technology. Zero-power technology puts the memories into Standby ...
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DSM2150F5V RESET TIMING AND DEVICE STATUS AT RESET Power On Reset Upon Power-up, the device requires a Reset ( ) pulse of duration t SET NLNH-PO steady. During this time period, the device loads internal configurations, clears some of the ...
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... Port E, TSTAT and TERR in addition to TMS, TCK, TDI and TDO. See Table 15. The FlashLINK ming cable available from STMicroelectronics for $USD59 and PSDsoft Express software that is available at no charge from www.st.com/psm is all that is needed to program a DSM device using the parallel port on any PC or laptop ...
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DSM2150F5V JTAG Extensions TSTAT and TERR are two JTAG extension signals (must be used as a pair) enabled by a command received over the four standard JTAG signals (TMS, TCK, TDI, and TDO) by PSDsoft Express. They are used to ...
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AC AND DC PARAMETERS These tables describe the AC and DC parameters of the device: DC Electrical Specification AC Timing Specification PLD Timing – Combinatorial Timing – Synchronous Clock Mode – Asynchronous Clock Mode – Input MicroCell Timing DSP Timing ...
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... Electrostatic Discharge Voltage (Human Body Model) ESD Note: 1. IPC/JEDEC J-STD-020A 2. JEDEC Std JESD22-A114A (C1=100pF, R1=1500 , R2=500 ) 52/73 plied. Exposure to Absolute Maximum Rating con- ditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality docu- ments. Parameter 1 or Hi- Min ...
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DC AND AC OPERATING AND MEASUREMENT CONDITIONS This section summarizes the operating and mea- surement conditions, and the DC and AC charac- teristics of the device. The parameters in the DC and AC Characteristic tables that follow are de- rived ...
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DSM2150F5V Figure 26. Switching Waveforms – Key WAVEFORMS Table 20. AC Symbols for PLD Timing Signal Letters A Address Input C CEout Output D Input Data E E Input N Reset Input or Output P Port Signal Output Q Output ...
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Table 21. DC Characteristics Symbol Parameter V High Level Input Voltage IH V Low Level Input Voltage IL V Reset High Level Input Voltage IH1 V Reset Low Level Input Voltage IL1 V Reset Pin Hysteresis HYS V (min) for ...
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DSM2150F5V Figure 27. Input to Output Disable / Enable INPUT INPUT TO OUTPUT ENABLE/DISABLE Table 22. CPLD Combinatorial Timing Symbol Parameter CPLD Input Pin/Feedback CPLD Combinatorial Output CPLD Input to CPLD Output t EA Enable CPLD Input ...
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Figure 28. Synchronous Clock Mode Timing – PLD CLKIN INPUT REGISTERED OUTPUT Table 23. CPLD MicroCell Synchronous Clock Mode Timing Symbol Parameter Maximum Frequency External Feedback Maximum Frequency f MAX Internal Feedback (f CNT Maximum Frequency Pipelined Data t Input ...
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DSM2150F5V Figure 29. Asynchronous Reset / Preset RESET/PRESET INPUT REGISTER OUTPUT Figure 30. Asynchronous Clock Mode Timing (Product Term Clock) CLOCK INPUT REGISTERED OUTPUT Table 24. CPLD MicroCell Asynchronous Clock Mode Timing Symbol Parameter Maximum Frequency External Feedback Maximum Frequency ...
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Figure 31. Input MicroCell Timing (Product Term Clock) PT CLOCK INPUT OUTPUT AI03101 Table 25. Input MicroCell Timing Symbol Parameter t Input Setup Time IS t Input Hold Time IH t NIB Input High Time INH t NIB Input Low ...
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DSM2150F5V Figure 32. READ Timing ADDRESS NON-MULTIPLEXED BUS DATA NON-MULTIPLEXED BUS CSI RD Table 26. READ Timing Symbol Parameter t Address Valid to Data Valid AVQV t CS Valid to Data Valid SLQV Data Valid 8-Bit Bus ...
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Figure 33. WRITE Timing ADDRESS NON-MULTIPLEXED BUS DATA NON-MULTIPLEXED BUS CSI WR Table 27. WRITE Timing Symbol Parameter t Address Valid to Leading Edge of WR AVWL t CS Valid to Leading Edge of WR SLWL t WR Data Setup ...
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DSM2150F5V Table 28. Flash Memory Program, WRITE and Erase Times Symbol 1 Flash Bulk Erase (pre-programmed) Flash Bulk Erase (not pre-programmed) t Sector Erase (pre-programmed) WHQV3 t Sector Erase (not pre-programmed) WHQV2 t Byte Program WHQV1 Program / Erase Cycles ...
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Figure 34. Reset (RESET) Timing V (min NLNH-PO Power-On Reset RESET Table 29. Reset (RESET) Timing Symbol Parameter t RESET Active Low Time NLNH t Power On Reset Active Low Time NLNH–PO t Warm Reset Active ...
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DSM2150F5V Figure 35. ISC Timing TCK TDI/TMS ISC OUTPUTS/TDO ISC OUTPUTS/TDO Table 30. ISC Timing Symbol t Clock (TCK, PC1) Frequency (except for PLD) ISCCF t Clock (TCK, PC1) High Time (except for PLD) ISCCH t Clock (TCK, PC1) Low ...
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PACKAGE MECHANICAL Figure 36. 80-lead, Plastic, Quad Flatpack, Package Outline QFP-A Note: Drawing is not to scale DSM2150F5V 65/73 ...
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DSM2150F5V Table 31. TQFP80 - 80-lead, Plastic, Quad Flatpack, Package Mechanical Data Symb. Typ 3.5° b 0.220 c D 14.000 D1 12.000 D2 9.500 E 14.000 E1 12.000 E2 9.500 e 0.500 L 0.600 L1 1.000 CP ...
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... PART NUMBERING Table 32. Ordering Information Scheme Example: Device Type DSM21=DSP System Memory for ADSP-21XXX Family DSM Series 50 = 4.25Mbit, Dual Array Flash, 40 I/O Main Flash Memory Density F5 = 4Mbit Operating Voltage ( 3.3V ± 10% Access Time 12 = 120nsec Package T = 80-pin TQFP Temperature Range 6 = –40 to 85°C (Industrial) For a list of available options (e ...
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DSM2150F5V APPENDIX A. TQFP80 PIN ASSIGNMENTS Table 33. Connections (Figure 3., page Pin Number Pin Assignments ...
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APPENDIX B. CSIOP REGISTER BIT DEFINITIONS Table 34. Data-In Registers – Ports Bit 7 Bit 6 Bit 5 Port pin 7 Port pin 6 Port pin 5 Note: Bit Definitions (Read only registers): Read ...
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DSM2150F5V Table 41. Output Macrocells A Register Bit 7 Bit 6 Bit 5 Mcella 7 Mcella 6 Mcella 5 Note: Bit Definitions: Write Register: Load MCellA7-MCellA0 with Read Register: Read MCellA7-MCellA0 output status. Table 42. Output Macrocells ...
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Table 48. Page Register Bit 7 Bit 6 Bit 5 PGR 7 PGR 6 PGR 5 Note: Bit Definitions: Configure Page input to PLD. Default is PGR7-PGR0=0. Table 49. PMMR0 Register Bit 7 Bit 6 Bit 5 not used not ...
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DSM2150F5V REVISION HISTORY Table 53. Document Revision History Date Rev. 14-Feb-2002 1.0 Document written 18-Sep-2002 1.1 JTAG Debug bus separated from JTAG ISP bus 11-Mar-2003 2.0 Document put in new template 09-Aug-04 3.0 Reformatted; correct block diagram, pin connections (Figure ...
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... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics ...