adsp-21535 STMicroelectronics, adsp-21535 Datasheet - Page 27
adsp-21535
Manufacturer Part Number
adsp-21535
Description
Dsm Digital Signal Processor System Memory For Analog Devices Dsps 3.3v Supply
Manufacturer
STMicroelectronics
Datasheet
1.ADSP-21535.pdf
(73 pages)
- Current page: 27 of 73
- Download datasheet (2Mb)
Complex PLD (CPLD)
The CPLD can be used to implement system logic
functions, such as loadable counters and shift reg-
isters, system mailboxes, handshaking protocols,
state machines, and random logic. See Applica-
tion Note AN1171 for details on how to specify log-
ic using PSDsoft Express.
The CPLD has the following blocks:
Figure 8. Macrocell and I/O Port
24 Input Macrocells (IMC)
16 Output Macrocells (OMC)
Product Term Allocator
AND Array capable of generating up to 190
product terms
Two I/O Ports.
Product Terms
from other
MacrocellS
PRODUCT TERM
PT
CLOCK
CLOCK
SELECT
PT CLEAR
GLOBAL
CLOCK
ALLOCATOR
PRODUCT TERMS
PT INPUT LATCH GATE/CLOCK
CPLD Macrocells
UP TO 10
POLARITY
SELECT
PT Output Enable ( OE )
Macrocell Feedback
I/O Port Input
PT PRESET
PR DI LD
D/T
CK
D/T/JK FF
SELECT
MCU DATA IN
CL
MCU LOAD
Q
DSP ADDRESS / DATA BUS
SELECT
COMB.
/REG
CONTROL
Macrocell
DATA
LOAD
Out to
MCU
Each of the blocks are described in the sections
that follow.
The IMCs and OMCs are connected to the device
internal data bus and can be directly accessed by
the DSP. This enables the DSP software to load
data into the OMC or read data from both the IMCs
and OMCs. This feature allows efficient implemen-
tation of system logic and eliminates the need to
connect the data bus to the AND Array as required
in most standard PLD macro cell architectures.
DATA
CPLD OUTPUT
I/O PORTS
WR
Input Macrocells
WR
PDR
D
D
REG.
DIR
INPUT
Q
Q
MUX
Q
Q D
D
G
DSM2150F5V
AI05770
I/O Pin
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