adsp-21535 STMicroelectronics, adsp-21535 Datasheet - Page 28

• Manufacturer Part Number: adsp-21535
• Description: Dsm Digital Signal Processor System Memory For Analog Devices Dsps 3.3v Supply
• Manufacturer: STMicroelectronics

DSM2150F5V
Output Macrocell (OMC)
Eight of the OMCs, McellA0-McellA7, are connect-
ed to Port A pins. The other eight Macrocells,
McellB0-McellB7, are connected to Ports B pins.
OMCs may be used for internal feedback (buried
registers), or their outputs may be routed to exter-
nal Port pins.
The OMC architecture is shown in
9., page
tive product terms available from the AND Array,
and borrowed product terms available (if unused)
from other OMC. The polarity of the product term
is controlled by the XOR gate. The OMC can im-
plement either sequential logic, using the flip-flop
element, or combinatorial logic. The multiplexer
Table 11. Output Macrocell Port and Data Bit Assignments
28/73
Macrocell
McellA0
McellA1
McellA2
McellA3
McellA4
McellA5
McellA6
McellA7
McellB0
McellB1
McellB2
McellB3
McellB4
McellB5
McellB6
McellB7
Output
30. As shown in the figure, there are na-
Assignment
Port A0
Port A1
Port A2
Port A3
Port A4
Port A5
Port A6
Port A7
Port B0
Port B1
Port B2
Port B3
Port B4
Port B5
Port B6
Port B7
Port
Native Product
Terms
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
Figure
Product Terms
Borrowed
Maximum
selects between the sequential or combinatorial
logic outputs. The multiplexer output can drive a
port pin and has a feedback path to the AND Array
inputs.
The flip-flop in the OMC block can be configured
as a D, T, JK, or SR type in PSDsoft Express
The flip-flop’s clock, preset, and clear inputs may
be driven from a product term of the AND Array.
Alternatively, CLKIN (PD1) can be used for the
clock input to the flip-flop. The flip-flop is clocked
on the rising edge of CLKIN (PD1). The preset and
clear are active High inputs. Each clear input can
use up to two product terms.
6
6
6
6
6
6
6
6
5
5
5
5
6
6
6
6
Reading in 16-bit
Data Bit for
Loading or
Mode
D10
D11
D12
D13
D14
D15
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
Reading in 8-bit
Data Bit for
Loading or
Mode
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
™
.