adsp-21535 STMicroelectronics, adsp-21535 Datasheet - Page 19

• Manufacturer Part Number: adsp-21535
• Description: Dsm Digital Signal Processor System Memory For Analog Devices Dsps 3.3v Supply
• Manufacturer: STMicroelectronics

INSTRUCTIONS
An instruction sequence consists of a sequence of
specific WRITE or READ operations.
IMPORTANT:
When the DSM2150F5V is configured for 8-bit op-
erations, all instruction sequences consist of byte
WRITE and READ operations on an even or odd
address boundary. Flash memory locations are
programmed in bytes to even or odd addresses.
When the DSM2150F5V is configured for 16-bit
operation, all instruction sequences consist of
word WRITE and READ operations on even ad-
dress boundaries only. The lower byte on D0-7 is
significant and the upper byte on D8-15 is ignored
during instructions and status. Flash memory loca-
tions are programmed in 16-bit words to even ad-
dresses only.
Each byte/word written to the device is received
and sequentially decoded and not executed as a
standard WRITE operation to the memory array
until the entire command string has been received.
The instruction sequence is executed when the
correct number of bytes/words are properly re-
ceived and the time between two consecutive
bytes/words is shorter than the time-out period,
t
tured to include READ operations after the initial
WRITE operations.
The instruction sequence must be followed exact-
ly. Any invalid combination of instruction bytes/
words or time-out between two consecutive bytes/
words while addressing Flash memory resets the
Table 7. Status Bit Definition
Note: 1. X = Not guaranteed value, can be read either ’1’ or ’0.’
TIMEOUT
Functional Block
Flash Memory
2. DQ7-DQ0 represent the Data Bus bits, D7-D0.
3. When the DSM2150F5V is configured for 16-bit operation, DQ8-DQ15 are not significant and can be ignored.
. Some instruction sequences are struc-
CSBOOT0-CSBOOT3
segment is selected)
Active (the desired
FS0-FS7, or
Polling
Data
DQ7
Toggle
DQ6
Flag
device logic into Read Array Mode (Flash memory
is read like a ROM device). The device supports
the instruction sequences summarized in
5., page 15
Flash memory:
For efficient decoding of the instruction sequenc-
es, the first two bytes/words of an instruction se-
quence are the coded cycles and are followed by
an instruction byte/word or confirmation byte/
word. The coded cycles consist of writing the data
AAh to address XX555h (or XXAAh to address
XXAAAh for 16-bit mode) during the first cycle and
data 55h to address XXAAAh (or XX55h to ad-
dress XX554 for 16-bit mode) during the second
cycle. Address input signals A12 and above are
“Don’t care” during the instruction sequence
WRITE cycles. However, the appropriate internal
Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3,
see Table 7) must be selected internally (active
low is logic ’1’).
Read memory contents
Read Main Flash Identifier value
Read Sector Protection Status
Program a Byte/Word
Erase memory by chip or sector
Suspend or resume sector erase
Reset to Read Array Mode
Unlock Bypass Instructions
Error
DQ5
Flag
and
DQ4
X
Table 6., page
Erase
Time-
DQ3
out
DQ2
X
17:
DSM2150F5V
DQ1
X
DQ0
Table
19/73
X