adsp-21535 STMicroelectronics, adsp-21535 Datasheet - Page 14

• Manufacturer Part Number: adsp-21535
• Description: Dsm Digital Signal Processor System Memory For Analog Devices Dsps 3.3v Supply
• Manufacturer: STMicroelectronics

DSM2150F5V
DETAILED OPERATION
Figure 4., page 10
of the device:
The following describes these functions in more
detail.
Flash Memories
The Main Flash memory array is divided into eight
equal 64 KByte sectors. The Secondary Flash
memory array is divided into four equal 8 KByte
sectors. Each sector is selected by the DPLD can
be separately protected from program and erase
cycles. This configuration is specified by using PS-
Dsoft Express
Memory Sector Select Signals. The DPLD gen-
erates the Select signals for all the internal memo-
ry blocks (see
twelve sectors of the Flash memories has a select
signal (FS0-FS7, or CSBOOT0-CSBOOT3) which
contains up to three product terms. Having three
product terms for each select signal allows a given
sector to be mapped into multiple areas of system
memory if needed.
Ready/Busy (PE4). This signal can be used to
output the Ready/
Busy
ray is being written, or when either Flash memory
array is being erased. The output is a ’1’ (Ready)
when no WRITE or Erase cycle is in progress. This
signal may be polled by the DSP or used as a DSP
interrupt to indicate when an erase or program cy-
cle is complete.
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Flash Memories
PLDs (DPLD, CPLD, Page Register)
DSP Bus Interface (Address, Data, Control)
I/O Ports
Runtime Control Registers
JTAG ISP Interface
is a ’0’ (Busy) when either Flash memory ar-
™
.
Figure 7., page
Busy
shows major functional areas
status of the device. Ready/
26). Each of the
Memory Operation. The Flash memories are ac-
cessed through the DSP Address, Data, and Con-
trol Bus Interface.
DSPs and MCUs cannot write to Flash memory as
it would an SRAM device. Flash memory must first
be “unlocked” with a special sequence of WRITE
operations to invoke an internal algorithm, then a
single data byte (or word if DSM2150F5V is con-
figured for 16-bit operation) is written to the Flash
memory array, then programming status is
checked by a READ operation or by checking the
Ready/
optionally may be bypassed by using the Unlock
Bypass command to reduce programming time.
Table 5., page 15
sequences to program (write) data to the Flash
memory arrays, erase the arrays, and check for
different types of status from the arrays when the
DSM2150F5V is configured to operate as an 8-bit
device. Table 6 lists instruction sequences when
the DSM2150F5V is configured for 16-bit opera-
tion. These instruction sequences are different
combinations of individual WRITE and READ op-
erations.
IMPORTANT: The DSP cannot read and execute
code from the same Flash memory array for which
it is directing an instruction sequence. Or more
simply stated, the DSP may not read code from
the same Flash array that is writing or erasing. In-
stead, the DSP must execute code from an alter-
nate memory (like its own internal SRAM or a
different Flash array) while sending instructions to
a given Flash array. Since the two Flash memory
arrays inside the DSM device are completely inde-
pendent, the DSP may read code from one array
while sending instructions to the other.
After a Flash memory array is programmed (writ-
ten) it will go to “Read Array” Mode, then the DSP
can read from Flash memory just as if would from
any ROM or SRAM device.
Busy
pin (PE4). This “unlocking” sequence
lists all of the special instruction