adsp-21535 STMicroelectronics, adsp-21535 Datasheet - Page 42

• Manufacturer Part Number: adsp-21535
• Description: Dsm Digital Signal Processor System Memory For Analog Devices Dsps 3.3v Supply
• Manufacturer: STMicroelectronics

DSM2150F5V
Figure 18. General Port Architecture
MCU I/O Mode
In MCU I/O Mode, DSP I/O Ports are expanded.
The DSP can read I/O pins, set the direction of I/O
pins, and change the state of I/O pins by access-
ing the registers in the csiop block. The csiop reg-
isters (Data In, Data Out, and Direction) that
implement MCU I/O Mode are defined
4., page 13
Data In Register for MCU I/O Mode. The
may read the Data In registers in the csiop block at
any time to determine the logic state of a Port pin.
This will be the state at the pin regardless of
whether it is driven by a source external to the
DSM or driven internally from the DSM device.
Reading a logic '0' for a bit in a Data In register
means the corresponding Port pin is also at logic
zero. Reading logic '1' means the pin is logic '1.'
Each bit in a Data In register corresponds to an in-
dividual Port pin. For a given Port, Bit 0 in a Data
In register corresponds to pin 0 of the Port. Exam-
ple, Bit 0 of the Data In register for Port B corre-
sponds to Port B pin PB0.
Data Out Register for MCU I/O Mode. The DSP
may write (or read) the Data Out register in the
csiop block at any time. Writing the Data Out reg-
42/73
and Appendix A.
Macrocell Outputs
EXT CS
WR
ENABLE PRODUCT TERM ( .OE )
WR
CPLD-INPUT
DATA OUT
READ MUX
DIR REG.
D
D
REG.
D
B
P
Q
Q
DATA IN
Table
DSP
DATA OUT
ister will change the logic state of a Port pin only if
it is not driven or controlled by the CPLD. Writing a
logic '0' to a bit in a Data Out register will force the
corresponding Port pin to be logic zero. Writing
logic one will drive the pin to logic one. Each bit in
the Data Out registers correspond to Port pins the
same way as the Data In registers described
above. When some pins of a Port are driven by the
CPLD, writing to the corresponding bit in a Data
Out register will have no effect as the CPLD over-
rides the Data Out register.
Direction Register for MCU I/O Mode. The Di-
rection Register, in conjunction with the output en-
able, controls the direction of data flow in the I/O
Ports. Any bit set to ’1’ in the Direction Register
causes the corresponding pin to be an output, and
any bit set to ’0’ causes it to be an input. The de-
fault mode for all port pins is input.
19., page 44
A, B and C. The direction of data flow for are con-
trolled not only by the direction register, but also by
the output enable product term from the PLD AND
Array. If the output enable product term is not ac-
tive, the Direction Register has sole control of a
given pin’s direction.
OUTPUT
shows the Port Architecture for Ports
MUX
ENABLE OUT
Macrocell
Input
PORT PIN
AI05772
Figure