XC2VP70 Xilinx, Inc., XC2VP70 Datasheet - Page 99

• Manufacturer Part Number: XC2VP70
• Description: Virtex-ii Pro Field Programmable Gate Array
• Manufacturer: Xilinx, Inc.

Virtex-II Pro Pin-to-Pin Input Parameter Guidelines
Global Clock Set-Up and Hold for LVCMOS25 Standard, Without DCM
,
Table 47: Global Clock Set-Up and Hold for LVCMOS25 Standard, Without DCM
42
Notes:
1. IFF = Input Flip-Flop or Latch
2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
3. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
Input Setup and Hold Time Relative to
Global Clock Input Signal for LVCMOS25
Standard.
For data input with different standards,
adjust the setup time delay by the values
shown in IOB Input Switching
Characteristics Standard
page
Full Delay
Global Clock and IFF without DCM
relative to the Global Clock input signal with the slowest route and heaviest load.
if a “0” is listed, there is no positive hold time.
22.
Description
Adjustments,
T
PSFD
Symbol
/T
PHFD
www.xilinx.com
1-800-255-7778
XC2VP100
XC2VP125
XC2VP20
XC2VP30
XC2VP40
XC2VP50
XC2VP70
XC2VP2
XC2VP4
XC2VP7
Device
-7
Speed Grade
2.70/–0.39
3.00/–0.70
2.80/–0.15
1.92/ 0.00
1.92/ 0.00
1.92/ 0.00
1.92/ 0.00
2.00/ 0.00
DS083-3 (v2.12) November 11, 2003
-6
Advance Product Specification
2.70/–0.39
3.00/–0.70
2.80/–0.15
1.92/ 0.00
1.92/ 0.00
1.92/ 0.00
1.92/ 0.00
2.00/ 0.00
-5
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R