XC2VP70 Xilinx, Inc., XC2VP70 Datasheet - Page 10

• Manufacturer Part Number: XC2VP70
• Description: Virtex-ii Pro Field Programmable Gate Array
• Manufacturer: Xilinx, Inc.

DS083-2 (v2.9) October 14, 2003
Virtex-II Pro Array Functional Description
This module describes the following Virtex-II Pro functional
components, as shown in
•
•
•
For a description of PPC405 embedded core programming
models and internal core operations, refer to the
Functional Description: RocketIO
Multi-Gigabit Transceiver (MGT)
This section summarizes the features of the RocketIO
multi-gigabit transceiver. For an in-depth discussion of the
RocketIO MGT, including digital and analog design consid-
erations, refer to the
Overview
The embedded RocketIO multi-gigabit transceiver is based
on Mindspeed’s SkyRail™ technology. Up to twenty-four
transceivers are available. The transceiver is designed to
operate at any baud rate in the range of 622 Mb/s to
3.125 Gb/s per channel. This includes specific baud rates
used by various standards as listed in
DS083-2 (v2.9) October 14, 2003
Advance Product Specification
Figure 1: Virtex-II Pro Generic Architecture Overview
Embedded RocketIO™ Multi-Gigabit Transceiver (MGT)
Processor block with embedded IBM
RISC CPU core (PPC405) and integration circuitry.
FPGA fabric based on Virtex-II architecture.
© 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
SelectIO™-Ultra
CLB
RocketIO Transceiver User
DCM
Figure
Configurable
Logic
CLB
CLB
Multi-Gigabit Transceiver
R
1:
RocketIO™
CLB
Table
DS083-1_01_010802
®
PowerPC™ 405
1.
PowerPC
Guide.
0
0
www.xilinx.com
1-800-255-7778
48
0
Virtex-II Pro™ Platform FPGAs:
Functional Description
Advance Product Specification
Processor Reference Guide
cessor Block Reference
transceiver digital/ analog design considerations, refer to
RocketIO Transceiver User
tion of the FPGA fabric (CLB, IOB, DCM, etc.), refer to the
Virtex-II Pro Platform FPGA User
All of the documents above, as well as a complete listing
and description of Xilinx-developed Intellectual Property
cores for Virtex-II Pro, are available on the Xilinx website at
www.xilinx.com/virtex2pro.
Virtex-II Pro Compared to Virtex-II Devices
Virtex-II Pro devices are built on the Virtex-II FPGA archi-
tecture. Most FPGA features are identical to Virtex-II
devices. Differences are described below:
•
•
•
•
•
Table 1: Protocols Supported by RocketIO Transceiver
Notes:
1.
Fibre Channel
Gigabit Ethernet
10Gbit Ethernet
Infiniband
Aurora
Custom Protocol
Virtex-II Pro MGT can support the 10G Fibre Channel data rates of
3.1875 Gb/s across 6" of standard FR-4 PCB and one connector
(Molex 74441 or equivalent) with a bit error rate of 10
The Virtex-II Pro FPGA family is the first to incorporate
embedded PPC405 cores and RocketIO MGTs.
V
3.3V as for Virtex-II devices. Advanced processing at
0.13 µm has resulted in a smaller die, faster speed,
and lower power consumption.
Virtex-II Pro devices are neither bitstream-compatible nor
pin-compatible with Virtex-II devices. However, Virtex-II
designs can be compiled into Virtex-II Pro devices.
SSTL3, AGP-2X/AGP, LVPECL_33, LVDS_33, and
LVDSEXT_33 standards are not supported.
The open-drain output pin TDO does not have an
internal pullup resistor.
Protocol
CCAUX
, the auxiliary supply voltage, is 2.5V instead of
1, 2, 3, 4, ...
1, 2, 3, 4, ...
Channels
(Lanes)
1, 4, 12
1
1
4
Guide. For detailed RocketIO
Guide. For a detailed descrip-
I/O Baud Rate
0.840 – 3.125
and the
up to 3.125
3.1875
(Gb/s)
3.125
1.06
2.12
1.25
2.5
Guide.
(1)
PowerPC 405 Pro-
Reference Clock
42.00 – 156.25
up to 156.25
-12
Rate (MHz)
159.375
156.25
or better.
62.5
106
125
53
1