XC2VP70 Xilinx, Inc., XC2VP70 Datasheet - Page 22

• Manufacturer Part Number: XC2VP70
• Description: Virtex-ii Pro Field Programmable Gate Array
• Manufacturer: Xilinx, Inc.

Functional Description: FPGA
Input/Output Blocks (IOBs)
Virtex-II Pro I/O blocks (IOBs) are provided in groups of two
or four on the perimeter of each device. Each IOB can be
used as input and/or output for single-ended I/Os. Two IOBs
can be used as a differential pair. A differential pair is always
connected to the same switch matrix, as shown in
IOB blocks are designed for high-performance I/O, support-
ing 22 single-ended standards, as well as differential sig-
naling with LVDS, LDT, bus LVDS, and LVPECL.
Note: Differential I/Os must use the same clock.
Supported I/O Standards
Virtex-II Pro IOB blocks feature SelectIO-Ultra inputs and out-
puts that support a wide variety of I/O signaling standards. In
addition to the internal supply voltage (V
put driver supply voltage (V
dard (see
(V
used. For exact supply voltage absolute maximum ratings,
see
Characteristics (Module
All of the user IOBs have fixed-clamp diodes to V
ground. The IOBs are not compatible or compliant with 5V
I/O standards (not 5V-tolerant).
DS083-2 (v2.9) October 14, 2003
Advance Product Specification
CCAUX
Virtex-II Pro™ Platform FPGAs: DC and Switching
Switch
Matrix
Figure 9: Virtex-II Pro Input/Output Tile
= 2.5V) is required, regardless of the I/O standard
Table 3
R
and
Table
3).
CCO
4). An auxiliary supply voltage
PAD4
PAD3
PAD2
PAD1
IOB
IOB
IOB
IOB
) is dependent on the I/O stan-
CCINT
Differential Pair
Differential Pair
DS083-2_30_010202
= 1.5V), out-
CCO
Figure
and to
www.xilinx.com
1-800-255-7778
9.
Table 5
trolled Impedance. See
(DCI), page
Table 3: Supported Single-Ended I/O Standards
Virtex-II Pro™ Platform FPGAs: Functional Description
Notes:
1.
2.
3.
4.
5. N/R = no requirement.
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
PCI33_3
PCI66_3
PCI-X
GTL
GTLP
HSTL_I
HSTL_II
HSTL_III
HSTL_IV
HSTL_I_18
HSTL_II_18
HSTL_III _18
HSTL_IV_18
SSTL2_I
SSTL2_II
SSTL18_I
SSTL18_II
Standard
Refer to
standards.
For PCI and PCI-X standards, refer to XAPP653.
V
voltage or the voltage seen at the I/O pad.
SSTL18_I is not a JEDEC-supported standard.
CCO
I/O
(1)
lists supported I/O standards with Digitally Con-
of GTL or GTLP should not be lower than the termination
(4)
XAPP659
(1)
19.
Output
Note (2)
Note (2)
Note (2)
Note (3)
Note (3)
V
3.3
3.3
2.5
1.8
1.5
1.5
1.5
1.5
1.5
1.8
1.8
1.8
1.8
2.5
2.5
1.8
1.8
CCO
for more details on interfacing to these 3.3V
Digitally Controlled Impedance
Note (2)
Note (2)
Note (2)
Note (3)
Note (3)
Input
V
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
3.3
3.3
2.5
1.8
1.5
CCO
Input
V
0.75
0.75
1.25
1.25
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
0.8
1.0
0.9
0.9
0.9
0.9
1.1
1.1
0.9
0.9
REF
Voltage (V
Termination
Board
0.75
0.75
1.25
1.25
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
1.2
1.5
1.5
1.5
0.9
0.9
1.8
1.8
0.9
0.9
TT
13
)