XC2VP70 Xilinx, Inc., XC2VP70 Datasheet - Page 34

• Manufacturer Part Number: XC2VP70
• Description: Virtex-ii Pro Field Programmable Gate Array
• Manufacturer: Xilinx, Inc.

The output from the function generator in each slice drives both the slice output and the D input of the storage element.
Figure 25
Configurations
Look-Up Table
Virtex-II Pro function generators are implemented as
4-input look-up tables (LUTs). Four independent inputs are
provided to each of the two function generators in a slice (F
and G). These function generators are each capable of
implementing any arbitrarily defined boolean function of four
inputs. The propagation delay is therefore independent of
the function implemented. Signals from the function gener-
ators can exit the slice (X or Y output), can input the XOR
dedicated gate (see arithmetic logic), or input the carry-logic
multiplexer (see fast look-ahead carry logic), or feed the D
input of the storage element, or go to the MUXF5 (not
shown in
DS083-2 (v2.9) October 14, 2003
Advance Product Specification
ALTDIG
SOPIN
SLICEWE[2:0]
WG4
WG3
WG2
WG1
CLK
CE
SR
G4
G3
G2
G1
BY
Figure
shows a more detailed view of a single slice.
R
SHIFTIN
25).
MULTAND
A4
A3
A2
A1
WG4
WG3
WG2
WG1
WE[2:0]
WE
CLK
Figure 25: Virtex-II Pro Slice (Top Half)
WSG
0
WS
WSF
Dual-Port
Shift-Reg
G
LUT
RAM
ROM
MC15
DI
D
SHIFTOUT
www.xilinx.com
1-800-255-7778
1
1
0
Shared between
x & y Registers
G2
PROD
G1
BY
In addition to the basic LUTs, the Virtex-II Pro slice contains
logic (MUXF5 and MUXFX multiplexers) that combines
function generators to provide any function of five, six,
seven, or eight inputs. The MUXFX is either MUXF6,
MUXF7, or MUXF8 according to the slice considered in the
CLB. Selected functions up to nine inputs (MUXF5 multi-
plexer) can be implemented in one slice. The MUXFX can
also be a MUXF6, MUXF7, or MUXF8 multiplexer to map
any function of six, seven, or eight inputs and selected wide
logic functions.
Register/Latch
The storage elements in a Virtex-II Pro slice can be config-
ured either as edge-triggered D-type flip-flops or as
level-sensitive latches. The D input can be directly driven by
Virtex-II Pro™ Platform FPGAs: Functional Description
MUXCY
COUT
CYOG
0
MUXCY
0
1
CIN
1
XORG
ORCY
DYMUX
CLK
YBMUX
CE
D
CE
CK
GYMUX
SR
SR
FF
LATCH
Y
REV
Q
DS031_01_112502
YB
Y
DY
DIG
SOPOUT
Q
25