XC2VP70 Xilinx, Inc., XC2VP70 Datasheet - Page 3

• Manufacturer Part Number: XC2VP70
• Description: Virtex-ii Pro Field Programmable Gate Array
• Manufacturer: Xilinx, Inc.

General Description
PowerPC RISC Block Features
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Virtex-II Pro Platform FPGA Technology
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Embedded 300+ MHz Harvard Architecture Block
Low Power Consumption: 0.9 mW/MHz
Five-Stage Data Path Pipeline
Hardware Multiply/Divide Unit
Thirty-Two 32-bit General Purpose Registers
16 KB Two-Way Set-Associative Instruction Cache
16 KB Two-Way Set-Associative Data Cache
Memory Management Unit (MMU)
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Dedicated On-Chip Memory (OCM) Interface
Supports IBM CoreConnect™ Bus Architecture
Debug and Trace Support
Timer Facilities
SelectRAM+ Memory Hierarchy
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Arithmetic Functions
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Flexible Logic Resources
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High-Performance Clock Management Circuitry
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Active Interconnect Technology
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SelectIO™-Ultra Technology
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64-entry unified Translation Look-aside Buffers (TLB)
Variable page sizes (1 KB to 16 MB)
Up to 10 Mb of True Dual-Port RAM in 18 Kb block
SelectRAM+ resources
Up to 1,738 Kb of distributed SelectRAM+
resources
High-performance interfaces to external memory
Dedicated 18-bit x 18-bit multiplier blocks
Fast look-ahead carry logic chains
Up to 111,232 internal registers/latches with Clock
Enable
Up to 111,232 look-up tables (LUTs) or cascadable
variable (1 to 16 bits) shift registers
Wide multiplexers and wide-input function support
Horizontal cascade chain and Sum-of-Products
support
Internal 3-state busing
Up to twelve Digital Clock Manager (DCM) modules
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16 global clock multiplexer buffers in all parts
Fourth-generation segmented routing structure
Fast, predictable routing delay, independent of
fanout
Deep sub-micron noise immunity benefits
Up to 1,200 user I/Os
Twenty-two single-ended standards and
six differential standards
XAPP653
Precise clock de-skew
Flexible frequency synthesis
High-resolution phase shifting
for more information.
www.xilinx.com
1-800-255-7778
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General Description
The Virtex-II Pro family contains platform FPGAs for
designs that are based on IP cores and customized mod-
ules. The family incorporates multi-gigabit transceivers and
PowerPC CPU blocks in Virtex-II Pro Series FPGA architec-
ture. It empowers complete solutions for telecommunica-
tion, wireless, networking, video, and DSP applications.
The leading-edge 0.13 µm CMOS nine-layer copper pro-
cess and Virtex-II Pro architecture are optimized for high
performance designs in a wide range of densities. Combin-
ing a wide variety of flexible features and IP cores, the
Virtex-II Pro family enhances programmable logic design
capabilities and is a powerful alternative to mask-pro-
grammed gate arrays.
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SRAM-Based In-System Configuration
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Supported by Xilinx Foundation™ and Alliance
Series™ Development Systems
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0.13 µm Nine-Layer Copper Process with 90 nm
High-Speed Transistors
1.5V (V
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IEEE 1149.1 Compatible Boundary-Scan Logic Support
Flip-Chip and Wire-Bond Ball Grid Array (BGA)
Packages in Standard 1.00 mm Pitch
Each Device 100% Factory Tested
CCAUX
Programmable LVCMOS sink/source current (2 mA
to 24 mA) per I/O
XCITE Digitally Controlled Impedance (DCI) I/O
PCI/ PCI-X support
Differential signaling
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Proprietary high-performance SelectLink
technology for communications between Xilinx
devices
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Fast SelectMAP™ configuration
Triple Data Encryption Standard (DES) security
option (bitstream encryption)
IEEE 1532 support
Partial reconfiguration
Unlimited reprogrammability
Readback capability
Integrated VHDL and Verilog design flows
ChipScope™ Integrated Logic Analyzer
CCINT
840 Mb/s Low-Voltage Differential Signaling I/O
(LVDS) with current mode drivers
Bus LVDS I/O
HyperTransport (LDT) I/O with current driver
buffers
Built-in DDR input and output registers
High-bandwidth data path
Double Data Rate (DDR) link
Web-based HDL generation methodology
auxiliary and V
) core power supply, dedicated 2.5V
CCO
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DS083-1 (v2.4.2) August 25, 2003
Advance Product Specification
I/O power supplies
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