XC2VP70 Xilinx, Inc., XC2VP70 Datasheet - Page 14

• Manufacturer Part Number: XC2VP70
• Description: Virtex-ii Pro Field Programmable Gate Array
• Manufacturer: Xilinx, Inc.

The receiver uses an elastic buffer, where "elastic" refers to
the ability to modify the read pointer for clock correction and
channel bonding.
Clock Correction
Clock RXRECCLK (the recovered clock) reflects the data
rate of the incoming data. Clock RXUSRCLK defines the
rate at which the FPGA fabric consumes the data. Ideally,
these rates are identical. However, since the clocks typically
have different sources, one of the clocks will be faster than
the other. The receiver buffer accommodates this difference
between the clock rates. See
Removable sequence
Nominally, the buffer is always half full. This is shown in the
top buffer,
ered data not yet read. Received data is inserted via the
write pointer under control of RXRECCLK. The FPGA fabric
reads data via the read pointer under control of RXUSR-
CLK. The half full/half empty condition of the buffer gives a
cushion for the differing clock rates. This operation contin-
ues indefinitely, regardless of whether or not "meaningful"
data is being received. When there is no meaningful data to
be received, the incoming data will consist of IDLE charac-
ters or other padding.
If RXUSRCLK is faster than RXRECCLK, the buffer
becomes more empty over time. The clock correction logic
corrects for this by decrementing the read pointer to reread
a repeatable byte sequence. This is shown in the middle
buffer,
the value represented by the dashed pointer. By decrement-
ing the read pointer instead of incrementing it in the usual
fashion, the buffer is partially refilled. The transceiver design
will repeat a single repeatable byte sequence when neces-
sary to refill a buffer. If the byte sequence length is greater
than one, and if attribute CLK_COR_REPEAT_WAIT is 0,
then the transceiver may repeat the same sequence multi-
ple times until the buffer is refilled to the desired extent.
Similarly, if RXUSRCLK is slower than RXRECCLK, the
buffer will fill up over time. The clock correction logic cor-
rects for this by incrementing the read pointer to skip over a
DS083-2 (v2.9) October 14, 2003
Advance Product Specification
Read
Figure
Figure 3: Clock Correction in Receiver
RXUSRCLK
Figure
R
Read
3, where the solid read pointer decrements to
Repeatable sequence
3, where the shaded area represents buff-
Read
Figure
Buffer less than half -full (emptying)
Buffer more than half-full (filling up)
"Nominal" condition: buffer half-full
Write
3.
RXRECCLK
Write
Write
DS083-2_15_100901
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removable byte sequence that need not appear in the final
FPGA fabric byte stream. This is shown in the bottom buffer,
Figure
value represented by the dashed pointer. This accelerates
the emptying of the buffer, preventing its overflow. The
transceiver design will skip a single byte sequence when
necessary to partially empty a buffer. If attribute
CLK_COR_REPEAT_WAIT is 0, the transceiver may also
skip two consecutive removable byte sequences in one step
to further empty the buffer when necessary.
These operations require the clock correction logic to recog-
nize a byte sequence that can be freely repeated or omitted
in the incoming data stream. This sequence is generally an
IDLE sequence, or other sequence comprised of special
values that occur in the gaps separating packets of mean-
ingful data. These gaps are required to occur sufficiently
often to facilitate the timely execution of clock correction.
Channel Bonding
Some gigabit I/O standards such as Infiniband specify the
use of multiple transceivers in parallel for even higher data
rates. Words of data are split into bytes, with each byte sent
over a separate channel (transceiver). See
The top half of the figure shows the transmission of words
split across four transceivers (channels or lanes). PPPP,
QQQQ, RRRR, SSSS, and TTTT represent words sent over
the four channels.
The bottom-left portion of
in the FPGA’s receivers at the other end of the four chan-
nels. Due to variations in transmission delay—especially if
the channels are routed through repeaters—the FPGA fab-
ric might not correctly assemble the bytes into complete
Virtex-II Pro™ Platform FPGAs: Functional Description
Full word SSSS sent over four channels, one byte per channel
Before channel bonding
3, where the solid read pointer increments to the
P Q R S T
Figure 4: Channel Bonding (Alignment)
P Q R S T
P Q R S T
P Q R S T
P Q R S T
P Q R S T
P Q R S T
P Q R S T
RXUSRCLK
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In Transmitters:
In Receivers:
Figure 4
Channel (lane) 0
Channel (lane) 1
Channel (lane) 2
Channel (lane) 3
shows the initial situation
After channel bonding
P Q R S T
RXUSRCLK
P Q R S T
P Q R S T
P Q R S T
Figure
Read
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4.
5