XC2VP70 Xilinx, Inc., XC2VP70 Datasheet - Page 15

• Manufacturer Part Number: XC2VP70
• Description: Virtex-ii Pro Field Programmable Gate Array
• Manufacturer: Xilinx, Inc.

Functional Description: RocketIO Multi-Gigabit Transceiver (MGT)
words. The bottom-left illustration shows the incorrect
assembly of data words PQPP, QRQQ, RSRR, and so forth.
To support correction of this misalignment, the data stream
includes special byte sequences that define corresponding
points in the several channels. In the bottom half of
Figure
characters. Each receiver recognizes the "P" channel bond-
ing character, and remembers its location in the buffer. At
some point, one transceiver designated as the master
instructs all the transceivers to align to the channel bonding
character "P" (or to some location relative to the channel
bonding character).
After this operation, words transmitted to the FPGA fabric
are properly aligned: RRRR, SSSS, TTTT, and so forth, as
shown in the bottom-right portion of
the channels remain properly aligned following the channel
bonding operation, the master transceiver must also control
the clock correction operations described in the previous
section for all channel-bonded transceivers.
Transmitter Buffer
The transmitter's buffer write pointer (TXUSRCLK) is fre-
quency-locked to its read pointer (REFCLK). Therefore,
clock correction and channel bonding are not required. The
purpose of the transmitter's buffer is to accommodate a
phase difference between TXUSRCLK and REFCLK. A
simple FIFO suffices for this purpose. A FIFO depth of four
will permit reliable operation with simple detection of over-
flow or underflow, which could occur if the clocks are not fre-
quency-locked.
CRC
The RocketIO transceiver CRC logic supports the 32-bit
invariant CRC calculation used by Infiniband, FibreChannel,
and Gigabit Ethernet.
On the transmitter side, the CRC logic recognizes where the
CRC bytes should be inserted and replaces four place-
holder bytes at the tail of a data packet with the computed
CRC. For Gigabit Ethernet and FibreChannel, transmitter
CRC may adjust certain trailing bytes to generate the
required running disparity at the end of the packet.
On the receiver side, the CRC logic verifies the received
CRC value, supporting the same standards as above.
The CRC logic also supports a user mode, with a simple
data
user-defined SOP and EOP characters.
Configuration
This section outlines functions that can be selected or con-
trolled by configuration. Xilinx implementation software sup-
ports 16 transceiver primitives, as shown in
Each of the primitives in
the configuration attributes, allowing some number of them
to be modified by the user. Refer to the RocketIO Trans-
ceiver User Guide for more details.
6
4, the shaded "P" bytes represent these special
packet
stucture
Table 2
beginning
defines default values for
Figure
and
4. To ensure that
Table
ending
2.
www.xilinx.com
1-800-255-7778
with
Table 2: Supported RocketIO Transceiver Protocol
Primitives
Reset
The receiver and transmitter have their own synchronous
reset inputs. The transmitter reset recenters the transmis-
sion FIFO, and resets all transmitter registers and the
8B/10B decoder. The receiver reset recenters the receiver
elastic buffer, and resets all receiver registers and the
8B/10B encoder. Neither reset has any effect on the PLLs.
Power
All RocketIO transceivers in the FPGA, whether instantiated
in the design or not, must be connected to power and
ground. Unused transceivers can be powered by any 2.5V
source, and passive filtering is not required.
Power Down
The Power Down module is controlled by the transceiver’s
POWERDOWN input pin. The Power Down pin on the
FPGA package has no effect on the transceiver.
Power Sequencing
Notes:
1. For more information on the Aurora protocol, visit
GT_CUSTOM
GT_FIBRE_CHAN_1
GT_FIBRE_CHAN_2
GT_FIBRE_CHAN_4
GT_ETHERNET_1
GT_ETHERNET_2
GT_ETHERNET_4
GT_XAUI_1
GT_XAUI_2
GT_XAUI_4
GT_INFINIBAND_1
GT_INFINIBAND_2
GT_INFINIBAND_4
GT_AURORA_1
GT_AURORA_2
GT_AURORA_4
http://www.xilinx.com.
(1)
(1)
(1)
Fully customizable by user
Fibre Channel, 1-byte data path
Fibre Channel, 2-byte data path
Fibre Channel, 4-byte data path
Gigabit Ethernet, 1-byte data path
Gigabit Ethernet, 2-byte data path
Gigabit Ethernet, 4-byte data path
10-gigabit Ethernet, 1-byte data path
10-gigabit Ethernet, 2-byte data path
10-gigabit Ethernet, 4-byte data path
Infiniband, 1-byte data path
Infiniband, 2-byte data path
Infiniband, 4-byte data path
1-byte data path
2-byte data path
4-byte data path
DS083-2 (v2.9) October 14, 2003
Advance Product Specification
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