XC2VP70 Xilinx, Inc., XC2VP70 Datasheet - Page 116

• Manufacturer Part Number: XC2VP70
• Description: Virtex-ii Pro Field Programmable Gate Array
• Manufacturer: Xilinx, Inc.

Table 4: Virtex-II Pro Pin Definitions (Continued)
BREFCLK Pin Definitions
These dedicated clocks use the same clock inputs for all packages:
DS083-4 (v2.5.5) August 25, 2003
Advance Product Specification
Notes:
1. All dedicated pins (JTAG and configuration) are powered by V
Other Pins
DXN, DXP
V
RSVD
V
V
V
GND
AVCCAUXRX#
AVCCAUXTX#
VTRXPAD#
VTTXPAD#
GNDA#
RXPPAD#
RXNPAD#
TXPPAD#
TXNPAD#
BATT
CCO
CCAUX
CCINT
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Pin Name
(2)
R
BREFCLK2
BREFCLK
Direction
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
N/A
N/A
N
N
P
P
GCLK5P
GCLK3P
GCLK4S
GCLK2S
Temperature-sensing diode pins (Anode: DXP, Cathode: DXN).
Decryptor key memory backup supply. (Do not connect if battery is not used.)
Reserved pin - do not connect.
Power-supply pins for the output drivers (per bank).
Power-supply pins for auxiliary circuits.
Power-supply pins for the internal core logic.
Ground.
Analog power supply for receive circuitry of the RocketIO multi-gigabit transceiver
(2.5V).
Analog power supply for transmit circuitry of the RocketIO multi-gigabit transceiver
(2.5V).
Receive termination supply for the RocketIO multi-gigabit transceiver (1.8V - 2.8V).
Transmit termination supply for the RocketIO multi-gigabit transceiver (1.8V - 2.8V).
Ground for the analog circuitry of the RocketIO multi-gigabit transceiver.
Positive differential receive port of the RocketIO multi-gigabit transceiver.
Negative differential receive port of the RocketIO multi-gigabit transceiver.
Positive differential transmit port of the RocketIO multi-gigabit transceiver.
Negative differential transmit port of the RocketIO multi-gigabit transceiver.
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BREFCLK2
BREFCLK
CCAUX
(independent of the bank V
Virtex-II Pro™ Platform FPGAs: Pinout Information
Description
N
N
P
P
GCLK6P
GCLK0P
GCLK7S
GCLK1S
CCO
voltage).
5