XC2VP70 Xilinx, Inc., XC2VP70 Datasheet - Page 74

• Manufacturer Part Number: XC2VP70
• Description: Virtex-ii Pro Field Programmable Gate Array
• Manufacturer: Xilinx, Inc.

Table 23: RocketIO Transmitter Switching Characteristics
DS083-3 (v2.12) November 11, 2003
Advance Product Specification
Notes:
1. Serial data rate in the -5 speed grade is limited to 2.0 Gb/s in both wirebond and flipchip packages.
2. UI = Unit Interval
3. Transmit latency delay TXDATA to TXP/TXN. Refer to
Serial data rate, full-speed clock
Serial data rate, half-speed clock
Serial data output deterministic jitter
Serial data output random jitter
TX rise time
TX fall time
Transmit latency
TXUSRCLK duty cycle
TXUSRCLK2 duty cycle
TXDATA[16:0]
TXUSRCLK2
R
TXP/TXN
Description
(3)
0
1
DATA ORIGINATES
2
Figure 5: Transmit Latency (Maximum, Including CRC)
. . . . .
Symbol
T
T
T
F
T
T
TX2DC
TXLAT
20
T
T
TXDC
GTX
RTX
FTX
DJ
RJ
1
21 22
RocketIO Transceiver User Guide
Virtex-II Pro™ Platform FPGAs: DC and Switching Characteristics
www.xilinx.com
1-800-255-7778
Wirebond packages
Wirebond packages
Flipchip packages
Flipchip packages
T
. . . . .
Excluding CRC
TXLAT
Including CRC
Conditions
20% – 80%
320
16
321 322
. . . . .
for more information on calculating latency.
0.600
0.600
Min
1.0
1.0
45
45
340 341 342
Typ
120
120
14
50
50
8
17
DATA ARRIVES
DS083-3_03_082301
3.125
2.5
Max
0.17
0.18
1.0
1.0
17
11
55
55
. . . .
(1)
(1)
TXUSR
Units
cycles
Gb/s
Gb/s
Gb/s
Gb/s
CLK
UI
UI
ps
ps
%
%
(2)
17