XC2VP70 Xilinx, Inc., XC2VP70 Datasheet - Page 46

• Manufacturer Part Number: XC2VP70
• Description: Virtex-ii Pro Field Programmable Gate Array
• Manufacturer: Xilinx, Inc.

Each SelectRAM+ memory and multiplier block is tied to
four switch matrices, as shown in
Association With Block SelectRAM+ Memory
The interconnect is designed to allow SelectRAM+ memory
and multiplier blocks to be used at the same time, but some
interconnect is shared between the SelectRAM+ and the
multiplier. Thus, SelectRAM+ memory can be used only up
to 18 bits wide when the multiplier is used, because the mul-
tiplier shares inputs with the upper data bits of the
SelectRAM+ memory.
This sharing of the interconnect is optimized for an
18-bit-wide block SelectRAM+ resource feeding the multi-
plier. The use of SelectRAM+ memory and the multiplier
with an accumulator in LUTs allows for implementation of a
digital signal processor (DSP) multiplier-accumulator (MAC)
function, which is commonly used in finite and infinite
impulse response (FIR and IIR) digital filters.
Configuration
The multiplier block is an 18-bit by 18-bit signed multiplier
(2's complement). Both A and B are 18-bit-wide inputs, and
the output is 36 bits.
DS083-2 (v2.9) October 14, 2003
Advance Product Specification
A[17:0]
B[17:0]
Figure 44: SelectRAM+ and Multiplier Blocks
Switch
Switch
Switch
Switch
Matrix
Matrix
Matrix
Matrix
R
Figure 45: Multiplier Block
Figure 45
MULT 18 x 18
Multiplier Block
18-Kbit block
SelectRAM
shows a multiplier block.
Figure
DS031_40_100400
44.
DS031_33_101000
P[35:0]
www.xilinx.com
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Locations / Organization
Multiplier organization is identical to the 18 Kb SelectRAM+
organization, because each multiplier is associated with an
18 Kb block SelectRAM+ resource.
Table 21: Multiplier Resources
In addition to the built-in multiplier blocks, the CLB elements
have dedicated logic to implement efficient multipliers in
logic. (Refer to
Global Clock Multiplexer Buffers
Virtex-II Pro devices have 16 clock input pins that can also
be used as regular user I/Os. Eight clock pads center on
both the top edge and the bottom edge of the device, as
illustrated in
The global clock multiplexer buffer represents the input to
dedicated low-skew clock tree distribution in Virtex-II Pro
devices. Like the clock pads, eight global clock multiplexer
buffers are on the top edge of the device and eight are on
the bottom edge.
Virtex-II Pro™ Platform FPGAs: Functional Description
XC2VP2
XC2VP4
XC2VP7
XC2VP20
XC2VP30
XC2VP40
XC2VP50
XC2VP70
XC2VP100
XC2VP125
Device
Figure 46: Virtex-II Pro Clock Pads
Figure
Configurable Logic Blocks (CLBs), page
Virtex-II Pro
Device
46.
8 clock pads
8 clock pads
Columns
10
12
14
16
18
4
4
6
8
8
DS083-2_42_052902
Total Multipliers
136
192
232
328
444
556
12
28
44
88
24).
37